From 4f732420526fdc1c969e910daca573dca72d7b82 Mon Sep 17 00:00:00 2001 From: Jon Murphy Date: Fri, 5 Aug 2022 15:43:44 -0600 Subject: treewide: Rename Sabrina to Mendocino 'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/amd/chausie/Kconfig | 4 ++-- src/mainboard/amd/chausie/devicetree.cb | 2 +- src/mainboard/google/skyrim/Kconfig | 2 +- src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | 4 ++-- src/mainboard/google/skyrim/variants/skyrim/overridetree.cb | 4 ++-- 5 files changed, 8 insertions(+), 8 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig index 477620ca47..e9fd743fbb 100644 --- a/src/mainboard/amd/chausie/Kconfig +++ b/src/mainboard/amd/chausie/Kconfig @@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select EC_ACPI - select SOC_AMD_SABRINA + select SOC_AMD_MENDOCINO select SOC_AMD_COMMON_BLOCK_USE_ESPI select AMD_SOC_CONSOLE_UART select MAINBOARD_HAS_CHROMEOS @@ -74,7 +74,7 @@ config RO_REGION_ONLY string depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A # Add the EFS and EC to the RO region only - # This is a chausie-specific override of soc/amd/sabrina/Kconfig + # This is a chausie-specific override of soc/amd/mendocino/Kconfig default "apu/amdfw apu/ecfw" config CHROMEOS diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index c0806a5c07..5cfd42f0f1 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -chip soc/amd/sabrina +chip soc/amd/mendocino register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, .generic_io_range[0] = { diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index f00775824f..e96940df03 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 select PSP_DISABLE_POSTCODES # TODO re-enable PSP postcodes later (b/227199049) - select SOC_AMD_SABRINA + select SOC_AMD_MENDOCINO select SOC_AMD_COMMON_BLOCK_USE_ESPI select TPM_GOOGLE_TI50 diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 71f1a5f510..9d4b12ceb0 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later -chip soc/amd/sabrina +chip soc/amd/mendocino # eSPI Configuration register "common_config.espi_config" = "{ @@ -213,4 +213,4 @@ chip soc/amd/sabrina device generic 3 on end end -end # chip soc/amd/sabrina +end # chip soc/amd/mendocino diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 89cc63cb0f..d8dc59bd45 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -26,7 +26,7 @@ fw_config end end -chip soc/amd/sabrina +chip soc/amd/mendocino device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller @@ -241,4 +241,4 @@ chip soc/amd/sabrina end end # UART1 -end # chip soc/amd/sabrina +end # chip soc/amd/mendocino -- cgit v1.2.3