From 4c81d4464f73f2d188e3d79a6a2ec6af6c256551 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 29 Jan 2018 12:14:37 +0100 Subject: mb/lenovo/x220: Allow optional use of the mrc.bin Besides the FSP codepath, Sandy Bridge has two codepaths, one native and one in the form of a binary. This allows the use of the binary. This can be useful to find flaws in the native raminit. The native raminit is still selected by default. Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/23489 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- src/mainboard/lenovo/x220/Kconfig | 1 - src/mainboard/lenovo/x220/romstage.c | 55 ++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 4b9451b6a8..73fb86030a 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_SANDYBRIDGE - select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index bdd251a708..e38dfe7e64 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -53,6 +54,55 @@ void mainboard_rcba_config(void) RCBA32(BUC) = 0; } +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pei_data_template = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0x00,0xa2,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .gbe_enable = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1333, + .usb_port_config = { + { 1, 0, 0x0040 }, + { 1, 1, 0x0080 }, + { 1, 3, 0x0080 }, + { 1, 3, 0x0080 }, + { 1, 0, 0x0080 }, + { 1, 0, 0x0080 }, + { 1, 2, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 6, 0x0080 }, + { 1, 5, 0x0080 }, + { 1, 6, 0x0080 }, + { 1, 6, 0x0080 }, + { 1, 7, 0x0080 }, + { 1, 6, 0x0080 }, + }, + }; + *pei_data = pei_data_template; +} + const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, 0 }, { 1, 1, 1 }, @@ -83,3 +133,8 @@ void mainboard_early_init(int s3resume) void mainboard_config_superio(void) { } + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} -- cgit v1.2.3