From 4c4a360018315b3bd60d3cfc3506137a631ee7ba Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Tue, 2 Feb 2021 13:04:33 +0800 Subject: soc/amd/picasso: clean up and re-sort UPD table Clean up the unused UPD and re-sort the table, and also update the new phy parameter in the soc code and overridetree. remove: EDpPhySel EDpVersion rename: DpPhyOverride -> edp_phy_override EDpPhySel -> edp_physel DpVsPemphLevel -> edp_dp_vs_pemph_level MarginDeemPh -> edp_margin_deemph Deemph6db4 -> edp_deemph_6db_4 BoostAdj -> edp_boost_adj eDP phy setting: DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004b COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80 BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- .../google/zork/variants/vilboz/overridetree.cb | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index c3afe1372a..ad5cc7e511 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -24,7 +24,17 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_offset" = "168" # eDP phy tuning settings - register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + register "edp_phy_override" = "ENABLE_EDP_TUNINGSET" + + # bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 + register "edp_physel" = "0x1" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x00, + .margin_deemph = 0x004b, + .deemph_6db4 = 0x0, + .boostadj = 0x80, + }" # eDP power sequence. all pwr sequence numbers below are in uint of 4ms, # and "0" as default value @@ -38,13 +48,6 @@ chip soc/amd/picasso register "pwrdown_bloff_to_varybloff" = "5" register "min_allowed_bl_level" = "0" - register "edp_tuningset" = "{ - .dp_vs_pemph_level = 0x0, - .deemph_6db4 = 0x004b, - .boostadj = 0x0, - .margin_deemph = 0x80, - }" - # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 -- cgit v1.2.3