From 4bab6e79b078c76d0a42883c4b4c9c68615d5a1e Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 3 May 2016 15:53:33 -0700 Subject: intel/sch: Merge northbridge and southbridge in src/soc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Vladimir Serbinenko --- src/mainboard/iwave/iWRainbowG6/Kconfig | 3 +- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 2 +- src/mainboard/iwave/iWRainbowG6/devicetree.cb | 49 +++++++++++++-------------- src/mainboard/iwave/iWRainbowG6/dsdt.asl | 9 +++-- src/mainboard/iwave/iWRainbowG6/romstage.c | 8 ++--- 5 files changed, 34 insertions(+), 37 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index 5e92cfb7dd..c441063dfd 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -4,8 +4,7 @@ if BOARD_IWAVE_RAINBOW_G6 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_441 - select NORTHBRIDGE_INTEL_SCH - select SOUTHBRIDGE_INTEL_SCH + select SOC_INTEL_SCH select HAVE_PIRQ_TABLE # select HAVE_MP_TABLE select UDELAY_LAPIC diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c index 1e42fa388d..a175e69ef0 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c +++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c @@ -25,7 +25,7 @@ #include #include -#include "southbridge/intel/sch/nvs.h" +#include "soc/intel/sch/nvs.h" void acpi_create_gnvs(global_nvs_t * gnvs) { diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb index 9addc14f3d..b13d87300b 100644 --- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb +++ b/src/mainboard/iwave/iWRainbowG6/devicetree.cb @@ -1,8 +1,18 @@ -chip northbridge/intel/sch +chip soc/intel/sch # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + # PIRQ routing + register "pirqa_routing" = "0xa" + register "pirqb_routing" = "0xb" + register "pirqc_routing" = "0x5" + register "pirqd_routing" = "0xf" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + device cpu_cluster 0 on chip cpu/intel/socket_441 device lapic 0 on end @@ -13,29 +23,18 @@ chip northbridge/intel/sch device pci 00.0 on end # host bridge device pci 02.0 on end # Integrated Graphics and Video Device - chip southbridge/intel/sch - register "pirqa_routing" = "0xa" - register "pirqb_routing" = "0xb" - register "pirqc_routing" = "0x5" - register "pirqd_routing" = "0xf" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - device pci 1a.0 on end # 26 0 USB Client - device pci 1b.0 on end # 27 0 HD Audio Controller - device pci 1c.0 on end # 28 0 PCI Express Port 1 - device pci 1c.1 on end # 28 1 PCI Express Port 2 - device pci 1d.0 on end # USB Classic UHCI Controller 1 - device pci 1d.1 on end # USB Classic UHCI Controller 2 - device pci 1d.2 on end # USB Classic UHCI Controller 3 - device pci 1d.7 on end # USB2 EHCI Controller - device pci 1e.0 on end # SDIO/MMC Port 0 - device pci 1e.1 on end # SDIO/MMC Port 1 - device pci 1e.2 on end # SDIO/MMC Port 2 - device pci 1f.0 on end # LPC bridge - device pci 1f.1 on end # PATA Controller - end + device pci 1a.0 on end # 26 0 USB Client + device pci 1b.0 on end # 27 0 HD Audio Controller + device pci 1c.0 on end # 28 0 PCI Express Port 1 + device pci 1c.1 on end # 28 1 PCI Express Port 2 + device pci 1d.0 on end # USB Classic UHCI Controller 1 + device pci 1d.1 on end # USB Classic UHCI Controller 2 + device pci 1d.2 on end # USB Classic UHCI Controller 3 + device pci 1d.7 on end # USB2 EHCI Controller + device pci 1e.0 on end # SDIO/MMC Port 0 + device pci 1e.1 on end # SDIO/MMC Port 1 + device pci 1e.2 on end # SDIO/MMC Port 2 + device pci 1f.0 on end # LPC bridge + device pci 1f.1 on end # PATA Controller end end diff --git a/src/mainboard/iwave/iWRainbowG6/dsdt.asl b/src/mainboard/iwave/iWRainbowG6/dsdt.asl index a33744577a..0dc46f2caa 100644 --- a/src/mainboard/iwave/iWRainbowG6/dsdt.asl +++ b/src/mainboard/iwave/iWRainbowG6/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", 0x02, // DSDT revision: ACPI v2.0 - "COREv2", // OEM id + "COREv4", // OEM id "COREBOOT", // OEM table id 0x20090419 // OEM revision ) @@ -26,7 +26,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include + #include // General Purpose Events //#include "acpi/gpe.asl" @@ -36,11 +36,10 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include - #include + #include } } /* Chipset specific sleep states */ - #include + #include } diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index c567a4acf3..37b442c0be 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -24,7 +24,7 @@ #include #if 0 #include "ram/ramtest.c" -#include "southbridge/intel/sch/early_smbus.c" +#include "soc/intel/sch/early_smbus.c" #endif #define RFID_TEST 0 @@ -268,9 +268,9 @@ int selectcard(void) } #endif -#include "northbridge/intel/sch/early_init.c" -#include -#include "northbridge/intel/sch/raminit.c" +#include "soc/intel/sch/early_init.c" +#include +#include "soc/intel/sch/raminit.c" static void sch_enable_lpc(void) { -- cgit v1.2.3