From 4714100c49663cee47cd37dbfe31e6ae11c4b6b4 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 14 Feb 2020 15:50:05 +0800 Subject: mb/google/drallion: Correct USB3 OC pin configuration USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly. BUG=b:147869924 TEST=USB function works well and OC function is corresponds to the right port. Signed-off-by: Eric Lai Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885 Reviewed-by: John Su Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 06d3e5dd26..92f3fb9772 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -154,9 +154,9 @@ chip soc/intel/cannonlake register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" -- cgit v1.2.3