From 3f1c5138fa14af673a05fa6f3d59926d64b5fe88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 20 Dec 2016 06:43:47 +0200 Subject: pcengines/apu1: Switch away from AGESA_LEGACY MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4bc357b202e6fc769dd4964a4bb774897e9fd20b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/18709 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/pcengines/apu1/Kconfig | 1 - src/mainboard/pcengines/apu1/romstage.c | 94 +++------------------------------ 2 files changed, 8 insertions(+), 87 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 347ad92f31..5e927cc95e 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -18,7 +18,6 @@ if BOARD_PCENGINES_APU1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 502341c44f..50b51cc5c0 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -15,100 +15,16 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include #include -#include -#include -#include -#include "SBPLATFORM.h" -#include "cbmem.h" -#include -#include #include #include #include "gpio_ftns.h" +#include "SB800.h" #define SIO_PORT 0x2e #define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -static void early_lpc_init(void); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - early_lpc_init(); - - - post_code(0x31); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ -} - static void early_lpc_init(void) { u32 mmio_base; @@ -141,3 +57,9 @@ static void early_lpc_init(void) configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); } + +void board_BeforeAgesa(struct sysinfo *cb) +{ + early_lpc_init(); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} -- cgit v1.2.3