From 397ce3c45fc8d2469c07565879c09d8fb00626ec Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 30 Oct 2019 17:06:58 +0100 Subject: vendorcode/eltan/security: Align mboot with coreboot tpm Align the eltan mboot support with coreboot tpm support to limit the amount of custom code. We now only support SHA256 pcrs, only single a single digest will be handled in a call. The pcr invalidation has been changed fixed values are now loaded while the correct algortihm is selected. BUG=N/A TEST=tested on fbg1701 Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/36483 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/facebook/fbg1701/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index c10e8666bf..b6ea03f969 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -78,7 +78,7 @@ static const uint8_t crtm_version[] = CONFIG_VENDORCODE_ELTAN_CRTM_VERSION_STRING COREBOOT_VERSION COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD; -int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) +int mb_crtm(void) { int status = TPM_E_IOERROR; TCG_PCR_EVENT2_HDR tcgEventHdr; @@ -91,9 +91,9 @@ int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) tcgEventHdr.eventSize = sizeof(crtm_version); printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); - status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, + status = mboot_hash_extend_log(0, (uint8_t *)crtm_version, tcgEventHdr.eventSize, &tcgEventHdr, - (uint8_t *)crtm_version, 0); + (uint8_t *)crtm_version); if (status) { printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); } -- cgit v1.2.3