From 38569d061099d6453adc2dfc11eb6a26fb1985a3 Mon Sep 17 00:00:00 2001 From: Bill XIE Date: Mon, 18 May 2020 17:18:43 +0800 Subject: mb/lenovo/{x230, x230s}: Disable SuperSpeed capabilities for WWAN USB Although on ThinkPads with Panther Point PCH the usb port inside wwan socket is usually wired to XHCI, it has actually no SuperSpeed lines, so maybe it is okay to disable SuperSpeed capabilities, and wire them to EHCI #2 by making use of XUSB2PRM and USB3PRM. This applies to both variants of x230. Change-Id: Ia8d27be84e4dbfa0efed506b9fc010e7f4d6ba23 Signed-off-by: Bill XIE Reviewed-on: https://review.coreboot.org/c/coreboot/+/41505 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x230/devicetree.cb | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 3a8e5fe852..085b4e137b 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,8 +58,9 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x0c15e1" register "gen4_dec" = "0x0c06a1" - register "xhci_switchable_ports" = "0xf" - register "superspeed_capable_ports" = "0xf" + # Do not enable xHCI Port 4 since WWAN USB is EHCI-only + register "xhci_switchable_ports" = "0x7" + register "superspeed_capable_ports" = "0x7" register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions -- cgit v1.2.3