From 35ef2e5606b51bc28fc295e01f72c4f37779b497 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 4 Jul 2023 08:44:23 +0530 Subject: =?UTF-8?q?mb/google/rex/var/ovis:=20Set=20TCC=20to=20100=C2=B0C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for ovis. BUG=b:270664854 TEST=Build and boot google/ovis. Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar Reviewed-by: Eric Lai --- src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 4e2c00ea10..4297c8714a 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -36,6 +36,9 @@ chip soc/intel/meteorlake # DPTF enable register "dptf_enable" = "1" + # Temporary setting TCC of 100C = Tj max (110) - TCC_Offset (10) + register "tcc_offset" = "10" + # Enable CNVi BT register "cnvi_bt_core" = "true" -- cgit v1.2.3