From 33f9633184ddc84151ab3685725d13448cdec232 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Tue, 23 Dec 2008 17:20:46 +0000 Subject: Handle RS690 quirks for 1 GHz noncoherent HyperTransport. The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor. Signed-off-by: Carl-Daniel Hailfinger Bao, Zheng says: As a matter of fact, both 600Mhz and 1Ghz have their own specific setting. This patch has been tested on dbm690t which HT link works on 800Mhz. Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/dbm690t/cache_as_ram_auto.c | 1 + src/mainboard/amd/pistachio/cache_as_ram_auto.c | 1 + 2 files changed, 2 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c index b691223b6d..6c8d9e3542 100644 --- a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c +++ b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c @@ -210,6 +210,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset); diff --git a/src/mainboard/amd/pistachio/cache_as_ram_auto.c b/src/mainboard/amd/pistachio/cache_as_ram_auto.c index 4ae241a7ef..52b5c0400a 100644 --- a/src/mainboard/amd/pistachio/cache_as_ram_auto.c +++ b/src/mainboard/amd/pistachio/cache_as_ram_auto.c @@ -213,6 +213,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset); post_code(0x06); -- cgit v1.2.3