From 325b92f64a62f355715a45470e41407ce3c39c1e Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 28 Feb 2012 00:24:15 +0200 Subject: Intel cpus: cache actual size of the Flash ROM device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/641 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering Reviewed-by: Patrick Georgi --- src/mainboard/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index a968b51563..051ae45dff 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -301,6 +301,10 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 +config CACHE_ROM_SIZE + hex + default ROM_SIZE + config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL default y if POWER_BUTTON_DEFAULT_ENABLE -- cgit v1.2.3