From 2c1c3138bc77928a1a9d9ac0ef0033c9c67b6fe3 Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Thu, 20 Jan 2022 17:31:39 +0100 Subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings Configure SATA, USB & HSIO settings per Atlas schematics v6. Signed-off-by: Lean Sheng Tan Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61277 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/prodrive/atlas/devicetree.cb | 43 +++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 9 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index cf2e27041e..ccda650a7b 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -8,6 +8,39 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # USB configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on device ref pcie5 on end device ref igpu on end @@ -19,18 +52,10 @@ chip soc/intel/alderlake device ref tbt_pcie_rp2 on end device ref tbt_pcie_rp3 on end device ref crashlog off end - device ref tcss_xhci on end - device ref tcss_dma0 on end - device ref tcss_dma1 on end device ref xhci on end device ref cnvi_wifi on end - device ref i2c0 on end - device ref i2c1 on end - device ref i2c2 on end - device ref i2c3 on end device ref heci1 on end device ref sata on end - device ref i2c5 on end device ref pcie_rp1 on end device ref pcie_rp3 on end # W/A to FSP issue device ref pcie_rp4 on end # W/A to FSP issue @@ -40,7 +65,7 @@ chip soc/intel/alderlake device ref pcie_rp9 on end device ref pcie_rp11 on end device ref uart0 on end - device ref gspi0 on end + device ref uart1 on end device ref p2sb on end device ref hda on end device ref smbus on end -- cgit v1.2.3