From 2bff1545985c9ada3adc78c23ddee259c17b4847 Mon Sep 17 00:00:00 2001 From: David Wu Date: Mon, 17 Jan 2022 15:56:53 +0800 Subject: =?UTF-8?q?mb/google/brya/var/brask:=20set=20tcc=5Foffset=20value?= =?UTF-8?q?=20to=2010=E2=84=83?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:214890058 BRANCH=None TEST=build pass Signed-off-by: David Wu Change-Id: I86acb172ed427d45973b9360e0413978cbd46645 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61142 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index a36c849779..466f08a21f 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -17,6 +17,8 @@ chip soc/intel/alderlake # DPTF enable register "dptf_enable" = "1" + register "tcc_offset" = "10" # TCC of 90 + # Enable CNVi BT register "CnviBtCore" = "true" -- cgit v1.2.3