From 2af14fee5278ac27b09b2ff104782ca0a79ee152 Mon Sep 17 00:00:00 2001
From: Jakub Czapiga <jacz@semihalf.com>
Date: Thu, 1 Jun 2023 12:31:10 +0000
Subject: mb/google/rex/variants/ovis: Add basic DTT

Add default Intel DPTF.

BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis

Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75580
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
---
 src/mainboard/google/rex/variants/ovis/overridetree.cb | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb
index 889ae0ed0b..bb138334cb 100644
--- a/src/mainboard/google/rex/variants/ovis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb
@@ -42,6 +42,11 @@ chip soc/intel/meteorlake
 	}"
 
 	device domain 0 on
+		device ref dtt on
+			chip drivers/intel/dptf
+				device generic 0 alias dptf_policy on end
+			end
+		end
 		device ref pcie_rp11 on
 			# Enable SSD Card PCIE 11 using clk 7
 			register "pcie_rp[PCH_RP(11)]" = "{
-- 
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