From 1e3e528d23e645c8c542aaa568a8e6e20aa00486 Mon Sep 17 00:00:00 2001
From: Chris Wang <chris.wang@amd.corp-partner.google.com>
Date: Tue, 23 Jun 2020 21:10:57 +0800
Subject: mb/google/zork: Apply USB2 default phy tune parameter for Zork family

Apply the default USB2 phy tuning parameter for Zork family

BUG=b:155132211
TEST=Build, verified the default value been applied on trembyle
and the USB2 device works well.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I1f00b04173796d70147e232bafa405487b0761e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/zork/variants/baseboard/devicetree.cb   | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)

(limited to 'src/mainboard')

diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb
index 159665f8b7..9db0d239d6 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb
@@ -60,6 +60,84 @@ chip soc/amd/picasso
 
 	register "xhci0_force_gen1" = "0"
 
+	# Controller0 Port0 Default
+	register "usb_2_port_0_tune_params" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0x6,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	# Controller0 Port1 Default
+	register "usb_2_port_1_tune_params" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0x6,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	# Controller0 Port2 Default
+	register "usb_2_port_2_tune_params" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0x6,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	# Controller0 Port3 Default
+	register "usb_2_port_3_tune_params" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0x6,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	# Controller1 Port0 Default
+	register "usb_2_port_4_tune_params" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x02,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0x5,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	# Controller1 Port1 Default
+	register "usb_2_port_5_tune_params" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x02,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0x5,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
 	# SPI Configuration
 	register "common_config.spi_config" = "{
 		.normal_speed = SPI_SPEED_66M, /* MHz */
-- 
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