From 1d29b7bbceed82a2161e249474086169ac3039f4 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 17 Nov 2019 02:43:08 +0100 Subject: mb/intel/dcp847ske: Disable xHCI via devicetree This is supported by generic PCH code now. Change-Id: Id5d764c97e47cdb08a68d03002ebebd996769914 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36901 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/intel/dcp847ske/devicetree.cb | 1 + src/mainboard/intel/dcp847ske/early_southbridge.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index ac152d85f9..6ed7c03120 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -39,6 +39,7 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + device pci 14.0 off end # USB xHCI device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 53f5564a97..1f76db8e52 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -31,7 +31,7 @@ void mainboard_late_rcba_config(void) { /* Disable devices */ - RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; + RCBA32(FD) |= PCH_DISABLE_P2P; #if CONFIG(USE_NATIVE_RAMINIT) /* Enable Gigabit Ethernet */ -- cgit v1.2.3