From 16d1eb68d2e8c72a9ce1bca59cde21cd58452e66 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 15 Jun 2023 14:28:47 +0200 Subject: soc/intel/apollolake: Switch to snake case for ModPhyIfValue For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyIfValue'. Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855 Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/baseboard/devicetree.cb | 2 +- src/mainboard/starlabs/lite/variants/glk/devicetree.cb | 2 +- src/mainboard/starlabs/lite/variants/glkr/devicetree.cb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index fdfcd61f51..c6bfe54e65 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -290,5 +290,5 @@ chip soc/intel/apollolake # FSP UPD to modify the Integrated Filter (IF) value # Set it to default value: 0x12 - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" end diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index abfbc0a6f6..2f58a7b5e5 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/apollolake register "pnp_settings" = "PNP_PERF_POWER" - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" register "prt0_gpio" = "GPIO_PRT0_UDEF" diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 3102b1fe29..fe32143c5d 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/apollolake register "pnp_settings" = "PNP_PERF_POWER" - register "ModPhyIfValue" = "0x12" + register "mod_phy_if_value" = "0x12" register "prt0_gpio" = "GPIO_PRT0_UDEF" -- cgit v1.2.3