From 161e731d7e6b3c23268c2f3916f2e0613741bc87 Mon Sep 17 00:00:00 2001 From: Robert Chen Date: Thu, 7 Apr 2022 16:10:31 +0800 Subject: mb/google/brya/var/vell: increase RFI Spread Spectrum to 6% Increase RFI Spread Spectrum to 6% for Vell as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:228929196 TEST=emerge-brya coreboot and pass RF test as before Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Signed-off-by: Robert Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/vell/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index fd5f27a6ff..a2fe72d239 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -71,6 +71,9 @@ chip soc/intel/alderlake register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" register "sagv" = "SaGv_Enabled" + # FIVR RFI Spread Spectrum 6% + register "fivr_spread_spectrum" = "FIVR_SS_6" + # I2C Port Config register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- cgit v1.2.3