From 106a3e8c7a3e0aba9d6e5a9c171d0e999063951a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Sep 2017 12:06:16 +0200 Subject: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21464 Reviewed-by: Felix Held Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/asrock/g41c-gs/romstage.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard') diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e9000a6fa7..4498b10706 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -75,6 +75,7 @@ static void ich7_enable_lpc(void) /* Decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); } void mainboard_romstage_entry(unsigned long bist) -- cgit v1.2.3