From 0e90dae584c506b06e7bf3d89064a64db04132bb Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Mon, 18 May 2015 10:29:06 +0200 Subject: Move TPM code out of chromeos This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/bolt/Kconfig | 1 + src/mainboard/google/butterfly/Kconfig | 1 + src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/link/romstage.c | 11 +++++------ src/mainboard/google/panther/Kconfig | 1 + src/mainboard/google/parrot/Kconfig | 1 + src/mainboard/google/parrot/romstage.c | 10 ++++------ src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/rambi/Kconfig | 1 + src/mainboard/google/samus/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/google/stout/Kconfig | 1 + src/mainboard/google/stout/romstage.c | 10 ++++------ src/mainboard/intel/baskingridge/Kconfig | 1 + src/mainboard/intel/emeraldlake2/romstage.c | 10 ++++------ src/mainboard/intel/wtm2/Kconfig | 1 + src/mainboard/samsung/lumpy/Kconfig | 1 + src/mainboard/samsung/lumpy/romstage.c | 10 ++++------ src/mainboard/samsung/stumpy/Kconfig | 1 + src/mainboard/samsung/stumpy/romstage.c | 10 ++++------ 21 files changed, 40 insertions(+), 36 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 2239f70a8d..74e1edda5f 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 7472c0668e..b1a64eebad 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index a8faaab3a6..5b97259217 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 316434fbb8..0f709255d2 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index ca8c2bd5ec..b345d5ec3e 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -41,9 +41,7 @@ #include #include #include "gpio.h" -#if CONFIG_CHROMEOS -#include -#endif +#include #include #include @@ -246,8 +244,9 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } + timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 31062edac2..37a8548f0a 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_INT15 select PHYSICAL_REC_SWITCH diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 07405c6098..9cf390ac79 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index d0fab67edb..a947c48666 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -39,10 +39,8 @@ #include #include #include "gpio.h" -#if CONFIG_CHROMEOS -#include -#endif #include +#include #include "ec/compal/ene932/ec.h" static void pch_enable_lpc(void) @@ -197,8 +195,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index d6a208bcbe..2c1560aad4 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 4c9e89144c..1130d11096 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select ALWAYS_LOAD_OPROM select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index f655b2969b..06317e9468 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select CHROMEOS_RAMOOPS_DYNAMIC select INTEL_INT15 diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index fd4cb2f588..cfbce5e4a3 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select EXTERNAL_MRC_BLOB select INTEL_DP select INTEL_DDI diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index ec03d8761e..eca83da637 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index ee6ca4f520..31b61e2d72 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -40,9 +40,7 @@ #include #include "gpio.h" #include -#if CONFIG_CHROMEOS -#include -#endif +#include #include #include #include "ec.h" @@ -251,8 +249,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index c3e336115e..f9161388dc 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index c9d5cf1f78..bcf498b7a4 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -39,10 +39,8 @@ #include #include #include +#include #include "gpio.h" -#if CONFIG_CHROMEOS -#include -#endif #define SIO_PORT 0x164e @@ -255,8 +253,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 5a064d1237..b8f616a1e8 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 7c9dce4ba7..fed4610533 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select CPU_INTEL_SOCKET_RPGA989 select EC_SMSC_MEC1308 select HAVE_ACPI_RESUME diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 9b1a023bfd..ce064bbe8b 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -45,9 +46,6 @@ #if CONFIG_DRIVERS_UART_8250IO #include #endif -#if CONFIG_CHROMEOS -#include -#endif static void pch_enable_lpc(void) { @@ -273,8 +271,8 @@ void main(unsigned long bist) } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 1eda8eb569..f749c3972f 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM select CPU_INTEL_SOCKET_RPGA989 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 6506c80a60..161c8d1f2d 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -41,13 +41,11 @@ #include #include #include +#include #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include #endif -#if CONFIG_CHROMEOS -#include -#endif /* Stumpy USB Reset Disable defined in cmos.layout */ #if CONFIG_USE_OPTION_TABLE @@ -283,8 +281,8 @@ void main(unsigned long bist) northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); -#if CONFIG_CHROMEOS - init_chromeos(boot_mode); -#endif + if (CONFIG_LPC_TPM) { + init_tpm(boot_mode == 2); + } timestamp_add_now(TS_END_ROMSTAGE); } -- cgit v1.2.3