From 0a2de7b538e3d6490a8d748bc8b8b9b7511c81bc Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 9 Dec 2019 11:12:08 +0900 Subject: mb/google/kohaku: Update TCC offset setting This change sets TCC offset to 10 for kohaku. BUG=b:144532818 BRANCH=firmware-hatch-12672.B TEST=Checked thermal and performance efficiency internally (b:144532818) Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/37587 Reviewed-by: Kane Chen Reviewed-by: Grace Kao Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index d515ecc44d..cd5ce0e816 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -2,8 +2,6 @@ chip soc/intel/cannonlake register "tdp_pl1_override" = "8" register "tdp_pl2_override" = "51" - register "tcc_offset" = "35" # TCC of 65C - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, -- cgit v1.2.3