From 0893b871c6335ffb2639415b419b2523a0d51c68 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 27 Oct 2021 17:52:35 -0600 Subject: mb/system76/gaze15: Convert to variant setup Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123 Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/system76/gaze15/Kconfig | 20 +- src/mainboard/system76/gaze15/Makefile.inc | 8 +- src/mainboard/system76/gaze15/board_info.txt | 2 - src/mainboard/system76/gaze15/bootblock.c | 5 +- src/mainboard/system76/gaze15/data.vbt | Bin 6144 -> 0 bytes src/mainboard/system76/gaze15/devicetree.cb | 29 +-- src/mainboard/system76/gaze15/dsdt.asl | 2 +- src/mainboard/system76/gaze15/gpio.c | 277 --------------------- src/mainboard/system76/gaze15/gpio_early.c | 17 -- src/mainboard/system76/gaze15/hda_verb.c | 26 -- .../system76/gaze15/include/mainboard/gpio.h | 9 - .../system76/gaze15/include/variant/gpio.h | 9 + src/mainboard/system76/gaze15/ramstage.c | 8 +- .../system76/gaze15/variants/gaze15/board_info.txt | 2 + .../system76/gaze15/variants/gaze15/data.vbt | Bin 0 -> 6144 bytes .../system76/gaze15/variants/gaze15/gpio.c | 277 +++++++++++++++++++++ .../system76/gaze15/variants/gaze15/gpio_early.c | 17 ++ .../system76/gaze15/variants/gaze15/hda_verb.c | 26 ++ .../gaze15/variants/gaze15/overridetree.cb | 31 +++ 19 files changed, 384 insertions(+), 381 deletions(-) delete mode 100644 src/mainboard/system76/gaze15/data.vbt delete mode 100644 src/mainboard/system76/gaze15/gpio.c delete mode 100644 src/mainboard/system76/gaze15/gpio_early.c delete mode 100644 src/mainboard/system76/gaze15/hda_verb.c delete mode 100644 src/mainboard/system76/gaze15/include/mainboard/gpio.h create mode 100644 src/mainboard/system76/gaze15/include/variant/gpio.h create mode 100644 src/mainboard/system76/gaze15/variants/gaze15/board_info.txt create mode 100644 src/mainboard/system76/gaze15/variants/gaze15/data.vbt create mode 100644 src/mainboard/system76/gaze15/variants/gaze15/gpio.c create mode 100644 src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c create mode 100644 src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c create mode 100644 src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb (limited to 'src/mainboard') diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig index e6265e40c2..e82a845283 100644 --- a/src/mainboard/system76/gaze15/Kconfig +++ b/src/mainboard/system76/gaze15/Kconfig @@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO select SOC_INTEL_CANNONLAKE_PCH_H - select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMETLAKE_1 if BOARD_SYSTEM76_GAZE15 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP @@ -25,45 +25,43 @@ config BOARD_SPECIFIC_OPTIONS config MAINBOARD_DIR default "system76/gaze15" +config VARIANT_DIR + default "gaze15" if BOARD_SYSTEM76_GAZE15 + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + config MAINBOARD_PART_NUMBER - default "gaze15" + default "gaze15" if BOARD_SYSTEM76_GAZE15 config MAINBOARD_SMBIOS_PRODUCT_NAME - string default "Gazelle" config MAINBOARD_VERSION - string - default "gaze15" + default "gaze15" if BOARD_SYSTEM76_GAZE15 config CBFS_SIZE default 0xA00000 config CONSOLE_POST - bool default y config ONBOARD_VGA_IS_PRIMARY - bool default y config UART_FOR_CONSOLE - int default 2 config MAX_CPUS - int default 16 config DIMM_MAX default 2 config VGA_BIOS_ID - string default "8086,9bc4" config POST_DEVICE - bool default n endif diff --git a/src/mainboard/system76/gaze15/Makefile.inc b/src/mainboard/system76/gaze15/Makefile.inc index 83ef3a5ca8..32a409992f 100644 --- a/src/mainboard/system76/gaze15/Makefile.inc +++ b/src/mainboard/system76/gaze15/Makefile.inc @@ -1,8 +1,10 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include bootblock-y += bootblock.c -bootblock-y += gpio_early.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += romstage.c ramstage-y += ramstage.c -ramstage-y += gpio.c -ramstage-y += hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/gaze15/board_info.txt b/src/mainboard/system76/gaze15/board_info.txt index 07130b5699..badfb66706 100644 --- a/src/mainboard/system76/gaze15/board_info.txt +++ b/src/mainboard/system76/gaze15/board_info.txt @@ -1,7 +1,5 @@ Vendor name: System76 -Board name: gaze15 Category: laptop -Release year: 2020 ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/system76/gaze15/bootblock.c b/src/mainboard/system76/gaze15/bootblock.c index ae416b4e77..b351fbd8ef 100644 --- a/src/mainboard/system76/gaze15/bootblock.c +++ b/src/mainboard/system76/gaze15/bootblock.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include +#include void bootblock_mainboard_early_init(void) { - mainboard_configure_early_gpios(); + variant_configure_early_gpios(); } diff --git a/src/mainboard/system76/gaze15/data.vbt b/src/mainboard/system76/gaze15/data.vbt deleted file mode 100644 index a97f225f04..0000000000 Binary files a/src/mainboard/system76/gaze15/data.vbt and /dev/null differ diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index f8e879db86..cf0965b3d5 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -22,14 +22,6 @@ chip soc/intel/cannonlake register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus - [PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console - }" - - # Misc register "AcousticNoiseMitigation" = "1" @@ -60,7 +52,6 @@ chip soc/intel/cannonlake end device domain 0 on - subsystemid 0x1558 0x8520 inherit device pci 00.0 on end # Host Bridge device pci 01.0 on # GPU Port # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) @@ -101,24 +92,6 @@ chip soc/intel/cannonlake end end device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end - end - end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 @@ -192,7 +165,7 @@ chip soc/intel/cannonlake device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface + device pci 1f.0 on # LPC Interface register "gen1_dec" = "0x00040069" register "gen2_dec" = "0x00fc0e01" register "gen3_dec" = "0x00fc0f01" diff --git a/src/mainboard/system76/gaze15/dsdt.asl b/src/mainboard/system76/gaze15/dsdt.asl index 8a3b4d7904..d2bd57d78a 100644 --- a/src/mainboard/system76/gaze15/dsdt.asl +++ b/src/mainboard/system76/gaze15/dsdt.asl @@ -7,7 +7,7 @@ DefinitionBlock( ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, - 0x20110725 /* OEM revision */ + 0x20110725 ) { #include diff --git a/src/mainboard/system76/gaze15/gpio.c b/src/mainboard/system76/gaze15/gpio.c deleted file mode 100644 index a9e6bb9c74..0000000000 --- a/src/mainboard/system76/gaze15/gpio.c +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -static const struct pad_config gpio_table[] = { - /* ------- GPIO Group GPD ------- */ - PAD_CFG_GPI(GPD0, NONE, PWROK), // PM_BATLOW# - PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT - PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP# - PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# - PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB# - PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC# - PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# (test point) - PAD_CFG_GPI(GPD7, NONE, PWROK), /* GPD_7 (crystal input, - low = signal ended, - high = differential) - */ - PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R - PAD_NC(GPD9, NONE), // PCH_SLP_WLAN# (test point) - PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC - PAD_NC(GPD11, NONE), // LAN_DISABLE_N (test point) - - /* ------- GPIO Group GPP_A ------- */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# - PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0 - PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1 - PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2 - PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3 - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ - _PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000), // INTP_OUT - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# - PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // CLK_PCI_KBC_R - PAD_NC(GPP_A10, NONE), - PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WUP# - PAD_NC(GPP_A12, NONE), // ISH_GP_6_R (test point) - PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE# - PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#_R - PAD_NC(GPP_A16, NONE), - PAD_NC(GPP_A17, NONE), - PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON - PAD_NC(GPP_A19, NONE), - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), // 3G_CONFIG2 (test point) - PAD_CFG_GPO(GPP_A22, 1, DEEP), // SATA_PWR_EN - PAD_NC(GPP_A23, NONE), // DGPU_PWM_SELECT# (test point) - - /* ------- GPIO Group GPP_B ------- */ - PAD_CFG_GPI(GPP_B0, NONE, DEEP),// TPM_PIRQ# - PAD_NC(GPP_B1, NONE), // GPP_B1 (test point) - PAD_NC(GPP_B2, NONE), // VRALERTB# (test point) - PAD_CFG_GPI(GPP_B3, NONE, DEEP), // BT_EN_PCH - PAD_CFG_GPI(GPP_B4, UP_20K, DEEP), // EXTTS_SNI_DRV1 - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_NC(GPP_B8, NONE), - PAD_NC(GPP_B9, NONE), - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ# - PAD_NC(GPP_B11, NONE), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // SPKR_SMC_EXTSMI (PCH_SPKR) - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_NC(GPP_B17, NONE), - PAD_CFG_GPI(GPP_B18, NONE, DEEP), // LPSS_GSPI0_MOSI (no reboot) - PAD_NC(GPP_B19, NONE), - PAD_NC(GPP_B20, NONE), - PAD_NC(GPP_B21, NONE), - PAD_CFG_GPI(GPP_B22, NONE, DEEP), // LPSS_GSPI1_MOSI (boot strap) - PAD_CFG_GPI(GPP_B23, NONE, DEEP), // PCH_HOT_GNSS_DISABLE - - /* ------- GPIO Group GPP_C ------- */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA - PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N - PAD_CFG_GPI(GPP_C3, NONE, DEEP), // SML0_CLK - PAD_CFG_GPI(GPP_C4, NONE, DEEP), // SMK0_DATA - PAD_NC(GPP_C5, NONE), // GPP_C5 (test point) - PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SMC_CPU_THERM - PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SMD_CPU_THERM - PAD_NC(GPP_C8, NONE), - PAD_NC(GPP_C9, NONE), - PAD_NC(GPP_C10, NONE), - PAD_NC(GPP_C11, NONE), - PAD_NC(GPP_C12, NONE), - PAD_NC(GPP_C13, NONE), - PAD_NC(GPP_C14, NONE), - PAD_NC(GPP_C15, NONE), - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_I2C - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_I2C - //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD - //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD - PAD_NC(GPP_C22, NONE), - PAD_NC(GPP_C23, NONE), - - /* ------- GPIO Group GPP_D ------- */ - PAD_NC(GPP_D0, NONE), - PAD_NC(GPP_D1, NONE), - PAD_NC(GPP_D2, NONE), - PAD_NC(GPP_D3, NONE), - PAD_CFG_GPI(GPP_D4, NONE, DEEP), // I2C2_SDA - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST# - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ - PAD_NC(GPP_D7, NONE), - PAD_NC(GPP_D8, NONE), - PAD_NC(GPP_D9, NONE), - PAD_NC(GPP_D10, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D12, NONE), - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_NC(GPP_D16, NONE), - PAD_NC(GPP_D17, NONE), // 100k pull down - PAD_NC(GPP_D18, NONE), - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // MIC_CLK_PCH_R - PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // MIC_DATA_PCH_R - PAD_NC(GPP_D21, NONE), - PAD_NC(GPP_D22, NONE), - PAD_CFG_GPI(GPP_D23, NONE, DEEP), // I2C2_SCL - - /* ------- GPIO Group GPP_E ------- */ - PAD_NC(GPP_E0, UP_20K), // SATAGP0 (test point) - PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1 - PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SATAGP2 - PAD_CFG_GPI(GPP_E3, NONE, DEEP), // EXTTS_SNI_DRV0 - PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0 - PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1 - PAD_NC(GPP_E6, NONE), // PCH_MUTE# (test point) - PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN# - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# - PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# - PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# - PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# - PAD_CFG_GPI(GPP_E12, NONE, DEEP), // VISACH2_D3 - - /* ------- GPIO Group GPP_F ------- */ - PAD_CFG_GPI(GPP_F0, NONE, DEEP), // SATAGP3 - PAD_NC(GPP_F1, NONE), - PAD_NC(GPP_F2, NONE), // ODD_DA#_R (test point) - PAD_NC(GPP_F3, NONE), // (test point) - PAD_NC(GPP_F4, NONE), - PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET - PAD_CFG_GPI(GPP_F6, NONE, DEEP), // DEVSLP4 - PAD_CFG_GPI(GPP_F7, NONE, DEEP), // LIGHT_KB_DET# - PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GPP_F8 - PAD_CFG_GPI(GPP_F9, NONE, DEEP), // GPP_F9 - PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC - PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD - PAD_CFG_GPI(GPP_F12, NONE, DEEP), // MFG_MODE - PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT - PAD_CFG_GPI(GPP_F14, NONE, DEEP), // 10k pull up to H_SKTOCC_N - PAD_CFG_GPI(GPP_F15, NONE, DEEP), // USB_OC4# - PAD_CFG_GPI(GPP_F16, NONE, DEEP), // USB_OC5# - PAD_CFG_GPI(GPP_F17, NONE, DEEP), // USB_OC6# - PAD_CFG_GPI(GPP_F18, NONE, DEEP), // USB_OC7# - //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS - //PAD_CFG_GPO(GPP_F22, 1, DEEP), // DGPU_RST#_PCH - //PAD_CFG_GPO(GPP_F23, 1, DEEP), // DGPU_PWR_EN - - /* ------- GPIO Group GPP_G ------- */ - PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), // BOARD_ID1 - PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2 - PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET - PAD_CFG_GPI(GPP_G3, NONE, DEEP), // GPIO4_1V8_MAIN_EN_R - PAD_CFG_GPI(GPP_G4, NONE, DEEP), // SMI#_R - PAD_NC(GPP_G5, NONE), - PAD_NC(GPP_G6, NONE), - PAD_NC(GPP_G7, NONE), - - /* ------- GPIO Group GPP_H ------- */ - PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ# - PAD_NC(GPP_H1, NONE), - PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ# - PAD_NC(GPP_H3, NONE), - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ# - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ# - PAD_NC(GPP_H6, NONE), - PAD_NC(GPP_H7, NONE), - PAD_NC(GPP_H8, NONE), - PAD_NC(GPP_H9, NONE), - PAD_NC(GPP_H10, UP_20K), // SML2CLK (test point) - PAD_NC(GPP_H11, UP_20K), // SML2DATA (test point) - PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 (eSPI flash sharing) - PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK - PAD_NC(GPP_H14, UP_20K), // SML3DATA (test point) - PAD_CFG_GPI(GPP_H15, NONE, DEEP), // SML3ALERT# - PAD_NC(GPP_H16, UP_20K), // SML4CLK (test point) - PAD_NC(GPP_H17, UP_20K), // SML4DATA (test point) - PAD_NC(GPP_H18, UP_20K), // SML4ALERT# (test point) - PAD_NC(GPP_H19, NONE), - PAD_NC(GPP_H20, NONE), - PAD_NC(GPP_H21, NONE), - PAD_NC(GPP_H22, NONE), - PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT# - - /* ------- GPIO Group GPP_I ------- */ - PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* I_MDP_HPD on 1660 Ti, - NC on 1650/1650 Ti - */ - PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD - PAD_CFG_GPI(GPP_I2, NONE, DEEP), // 1k pull to MDP_E_HPD - PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // 1k pull to MDP_E_HPD - PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD - PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* I_MDP_CLK (on 1660 Ti), - NC (on 1650/1650 Ti) - */ - PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* I_MDP_DATA (on 1660 Ti), - NC (on 1650/1650 Ti) - */ - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* HDMI_CTRLCLK (on 1650/1650 Ti), - test point (on 1660 Ti) - */ - PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* HDMI_CTRLDATA (on 1650/1650 Ti), - test point (on 1660 Ti) - */ - PAD_NC(GPP_I9, NONE), - PAD_NC(GPP_I10, NONE), - PAD_CFG_GPI(GPP_I11, NONE, DEEP), // 10k pull up to H_SKTOCC_N - PAD_NC(GPP_I12, NONE), - PAD_NC(GPP_I13, NONE), - PAD_NC(GPP_I14, NONE), - - /* ------- GPIO Group GPP_J ------- */ - PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING - PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // GPP_J1 - PAD_NC(GPP_J2, NONE), // 100k pull down - PAD_NC(GPP_J3, NONE), // 100k pull down - PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT - PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP - PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT - PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP - PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD - PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD - PAD_NC(GPP_J10, NONE), - PAD_NC(GPP_J11, NONE), // 75k pull down - - /* ------- GPIO Group GPP_K ------- */ - PAD_NC(GPP_K0, NONE), // PCH_GPPK0_PCH_PEXVDD_EN (test point) - PAD_NC(GPP_K1, NONE), // PCH_GPPK1_PCH_FBVDDQ_EN (test point) - PAD_NC(GPP_K2, NONE), // PCH_GPPK2_PCH_1V8RUN_EN (test point) - _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x0000), // SCI#_R - PAD_NC(GPP_K4, NONE), - PAD_NC(GPP_K5, NONE), - _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_R - PAD_NC(GPP_K7, NONE), - PAD_CFG_GPO(GPP_K8, 1, DEEP), // SATA_M2_PWR_EN1 - PAD_CFG_GPO(GPP_K9, 1, DEEP), // SATA_M2_PWR_EN2 - PAD_NC(GPP_K10, NONE), // PCH_GPPK10_PCH_NVVDD_EN (test point) - PAD_NC(GPP_K11, NONE), // PCH_GPPK11_PCH_NVVDD_EN (test point) - PAD_NC(GPP_K12, NONE), // (test point) - PAD_NC(GPP_K13, NONE), - PAD_CFG_GPO(GPP_K14, 0, DEEP), // GPP_K14_TEST_R - PAD_NC(GPP_K15, NONE), - PAD_NC(GPP_K16, NONE), // (test point) - PAD_NC(GPP_K17, NONE), - PAD_NC(GPP_K18, NONE), - PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_RR - PAD_CFG_GPO(GPP_K20, 1, DEEP), // GPU_EVENT# - PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH - PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R - PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT# -}; - -void mainboard_configure_gpios(void) -{ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} diff --git a/src/mainboard/system76/gaze15/gpio_early.c b/src/mainboard/system76/gaze15/gpio_early.c deleted file mode 100644 index 881af89e57..0000000000 --- a/src/mainboard/system76/gaze15/gpio_early.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -static const struct pad_config early_gpio_table[] = { - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD - PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH - PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN -}; - -void mainboard_configure_early_gpios(void) -{ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} diff --git a/src/mainboard/system76/gaze15/hda_verb.c b/src/mainboard/system76/gaze15/hda_verb.c deleted file mode 100644 index 1540485862..0000000000 --- a/src/mainboard/system76/gaze15/hda_verb.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -const u32 cim_verb_data[] = { - /* Realtek, ALC293 */ - 0x10ec0293, /* Vendor ID */ - 0x15588520, /* Subsystem ID */ - 12, /* Number of entries */ - AZALIA_SUBVENDOR(0, 0x15588520), - AZALIA_PIN_CFG(0, 0x12, 0x90a60130), - AZALIA_PIN_CFG(0, 0x13, 0x40000000), - AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x02a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x41738205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), -}; - -const u32 pc_beep_verbs[] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/gaze15/include/mainboard/gpio.h b/src/mainboard/system76/gaze15/include/mainboard/gpio.h deleted file mode 100644 index c6393beebb..0000000000 --- a/src/mainboard/system76/gaze15/include/mainboard/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -void mainboard_configure_early_gpios(void); -void mainboard_configure_gpios(void); - -#endif diff --git a/src/mainboard/system76/gaze15/include/variant/gpio.h b/src/mainboard/system76/gaze15/include/variant/gpio.h new file mode 100644 index 0000000000..95d576294f --- /dev/null +++ b/src/mainboard/system76/gaze15/include/variant/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/gaze15/ramstage.c b/src/mainboard/system76/gaze15/ramstage.c index ae2d7414d8..ca6f64b158 100644 --- a/src/mainboard/system76/gaze15/ramstage.c +++ b/src/mainboard/system76/gaze15/ramstage.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include +#include -static void init_mainboard(void *chip_info) +static void mainboard_init(void *chip_info) { - mainboard_configure_gpios(); + variant_configure_gpios(); } struct chip_operations mainboard_ops = { - .init = init_mainboard, + .init = mainboard_init, }; diff --git a/src/mainboard/system76/gaze15/variants/gaze15/board_info.txt b/src/mainboard/system76/gaze15/variants/gaze15/board_info.txt new file mode 100644 index 0000000000..a574325e75 --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/board_info.txt @@ -0,0 +1,2 @@ +Board name: gaze15 +Release year: 2020 diff --git a/src/mainboard/system76/gaze15/variants/gaze15/data.vbt b/src/mainboard/system76/gaze15/variants/gaze15/data.vbt new file mode 100644 index 0000000000..a97f225f04 Binary files /dev/null and b/src/mainboard/system76/gaze15/variants/gaze15/data.vbt differ diff --git a/src/mainboard/system76/gaze15/variants/gaze15/gpio.c b/src/mainboard/system76/gaze15/variants/gaze15/gpio.c new file mode 100644 index 0000000000..b7ae347d37 --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/gpio.c @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_GPI(GPD0, NONE, PWROK), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB# + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC# + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# (test point) + PAD_CFG_GPI(GPD7, NONE, PWROK), /* GPD_7 (crystal input, + low = signal ended, + high = differential) + */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK_R + PAD_NC(GPD9, NONE), // PCH_SLP_WLAN# (test point) + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC + PAD_NC(GPD11, NONE), // LAN_DISABLE_N (test point) + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST# + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // LPC_AD0 + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // LPC_AD1 + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // LPC_AD2 + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // LPC_AD3 + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME# + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ + _PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000), // INTP_OUT + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // CLK_PCI_KBC_R + PAD_NC(GPP_A10, NONE), + PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WUP# + PAD_NC(GPP_A12, NONE), // ISH_GP_6_R (test point) + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), // SUSWARN# + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // S4_STATE# + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), // SUS_PWR_ACK#_R + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPO(GPP_A18, 1, DEEP), // SB_BLON + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), // 3G_CONFIG2 (test point) + PAD_CFG_GPO(GPP_A22, 1, DEEP), // SATA_PWR_EN + PAD_NC(GPP_A23, NONE), // DGPU_PWM_SELECT# (test point) + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPI(GPP_B0, NONE, DEEP),// TPM_PIRQ# + PAD_NC(GPP_B1, NONE), // GPP_B1 (test point) + PAD_NC(GPP_B2, NONE), // VRALERTB# (test point) + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // BT_EN_PCH + PAD_CFG_GPI(GPP_B4, UP_20K, DEEP), // EXTTS_SNI_DRV1 + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // SPKR_SMC_EXTSMI (PCH_SPKR) + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPI(GPP_B18, NONE, DEEP), // LPSS_GSPI0_MOSI (no reboot) + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_CFG_GPI(GPP_B22, NONE, DEEP), // LPSS_GSPI1_MOSI (boot strap) + PAD_CFG_GPI(GPP_B23, NONE, DEEP), // PCH_HOT_GNSS_DISABLE + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N + PAD_CFG_GPI(GPP_C3, NONE, DEEP), // SML0_CLK + PAD_CFG_GPI(GPP_C4, NONE, DEEP), // SMK0_DATA + PAD_NC(GPP_C5, NONE), // GPP_C5 (test point) + PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SMC_CPU_THERM + PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SMD_CPU_THERM + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_I2C + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_I2C + //PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + //PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI(GPP_D4, NONE, DEEP), // I2C2_SDA + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RF_RST# + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), // 100k pull down + PAD_NC(GPP_D18, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // MIC_CLK_PCH_R + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // MIC_DATA_PCH_R + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_CFG_GPI(GPP_D23, NONE, DEEP), // I2C2_SCL + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, UP_20K), // SATAGP0 (test point) + PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1 + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SATAGP2 + PAD_CFG_GPI(GPP_E3, NONE, DEEP), // EXTTS_SNI_DRV0 + PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0 + PAD_CFG_GPI(GPP_E5, NONE, DEEP), // DEVSLP1 + PAD_NC(GPP_E6, NONE), // PCH_MUTE# (test point) + PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# + PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# + PAD_CFG_GPI(GPP_E12, NONE, DEEP), // VISACH2_D3 + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPI(GPP_F0, NONE, DEEP), // SATAGP3 + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), // ODD_DA#_R (test point) + PAD_NC(GPP_F3, NONE), // (test point) + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI(GPP_F5, NONE, DEEP), // KBLED_DET + PAD_CFG_GPI(GPP_F6, NONE, DEEP), // DEVSLP4 + PAD_CFG_GPI(GPP_F7, NONE, DEEP), // LIGHT_KB_DET# + PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GPP_F8 + PAD_CFG_GPI(GPP_F9, NONE, DEEP), // GPP_F9 + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC + PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD + PAD_CFG_GPI(GPP_F12, NONE, DEEP), // MFG_MODE + PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT + PAD_CFG_GPI(GPP_F14, NONE, DEEP), // 10k pull up to H_SKTOCC_N + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // USB_OC4# + PAD_CFG_GPI(GPP_F16, NONE, DEEP), // USB_OC5# + PAD_CFG_GPI(GPP_F17, NONE, DEEP), // USB_OC6# + PAD_CFG_GPI(GPP_F18, NONE, DEEP), // USB_OC7# + //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + //PAD_CFG_GPO(GPP_F22, 1, DEEP), // DGPU_RST#_PCH + //PAD_CFG_GPO(GPP_F23, 1, DEEP), // DGPU_PWR_EN + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), // BOARD_ID1 + PAD_CFG_GPI(GPP_G1, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPI(GPP_G2, NONE, DEEP), // TPM_DET + PAD_CFG_GPI(GPP_G3, NONE, DEEP), // GPIO4_1V8_MAIN_EN_R + PAD_CFG_GPI(GPP_G4, NONE, DEEP), // SMI#_R + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_NC(GPP_H1, NONE), + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // PEG_CLKREQ# + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_CLKREQ# + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // SSD2_CLKREQ# + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, UP_20K), // SML2CLK (test point) + PAD_NC(GPP_H11, UP_20K), // SML2DATA (test point) + PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H_12 (eSPI flash sharing) + PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK + PAD_NC(GPP_H14, UP_20K), // SML3DATA (test point) + PAD_CFG_GPI(GPP_H15, NONE, DEEP), // SML3ALERT# + PAD_NC(GPP_H16, UP_20K), // SML4CLK (test point) + PAD_NC(GPP_H17, UP_20K), // SML4DATA (test point) + PAD_NC(GPP_H18, UP_20K), // SML4ALERT# (test point) + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT# + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), /* I_MDP_HPD on 1660 Ti, + NC on 1650/1650 Ti + */ + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // HDMI_HPD + PAD_CFG_GPI(GPP_I2, NONE, DEEP), // 1k pull to MDP_E_HPD + PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // 1k pull to MDP_E_HPD + PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // EDP_HPD + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), /* I_MDP_CLK (on 1660 Ti), + NC (on 1650/1650 Ti) + */ + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), /* I_MDP_DATA (on 1660 Ti), + NC (on 1650/1650 Ti) + */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* HDMI_CTRLCLK (on 1650/1650 Ti), + test point (on 1660 Ti) + */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* HDMI_CTRLDATA (on 1650/1650 Ti), + test point (on 1660 Ti) + */ + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, DEEP), // 10k pull up to H_SKTOCC_N + PAD_NC(GPP_I12, NONE), + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), // GPP_J1 + PAD_NC(GPP_J2, NONE), // 100k pull down + PAD_NC(GPP_J3, NONE), // 100k pull down + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), // 75k pull down + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), // PCH_GPPK0_PCH_PEXVDD_EN (test point) + PAD_NC(GPP_K1, NONE), // PCH_GPPK1_PCH_FBVDDQ_EN (test point) + PAD_NC(GPP_K2, NONE), // PCH_GPPK2_PCH_1V8RUN_EN (test point) + _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x0000), // SCI#_R + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#_R + PAD_NC(GPP_K7, NONE), + PAD_CFG_GPO(GPP_K8, 1, DEEP), // SATA_M2_PWR_EN1 + PAD_CFG_GPO(GPP_K9, 1, DEEP), // SATA_M2_PWR_EN2 + PAD_NC(GPP_K10, NONE), // PCH_GPPK10_PCH_NVVDD_EN (test point) + PAD_NC(GPP_K11, NONE), // PCH_GPPK11_PCH_NVVDD_EN (test point) + PAD_NC(GPP_K12, NONE), // (test point) + PAD_NC(GPP_K13, NONE), + PAD_CFG_GPO(GPP_K14, 0, DEEP), // GPP_K14_TEST_R + PAD_NC(GPP_K15, NONE), + PAD_NC(GPP_K16, NONE), // (test point) + PAD_NC(GPP_K17, NONE), + PAD_NC(GPP_K18, NONE), + PAD_CFG_GPI(GPP_K19, NONE, DEEP), // SMI#_RR + PAD_CFG_GPO(GPP_K20, 1, DEEP), // GPU_EVENT# + PAD_CFG_GPI(GPP_K21, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_CFG_GPI(GPP_K22, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PRSNT# +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c b/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c new file mode 100644 index 0000000000..38b1bc4374 --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c new file mode 100644 index 0000000000..1540485862 --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15588520, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15588520), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41738205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb new file mode 100644 index 0000000000..1185223ec8 --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb @@ -0,0 +1,31 @@ +chip soc/intel/cannonlake + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus + [PchSerialIoIndexI2C1] = PchSerialIoPci, // USB-C + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console + }" + + device domain 0 on + subsystemid 0x1558 0x8520 inherit + + device pci 15.0 on # I2C0 + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + end +end -- cgit v1.2.3