From 040553f262bb34f6a51362e1f1fcad3fa91bfe9a Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Tue, 23 Feb 2010 10:18:43 +0000 Subject: Adjust msi/ms7135 DCACHE_RAM_* config to previous 32KiB values, 4KiB is not enough to work. Additionally, modify the device tree so that the undocumented LDN 6 is ignored by the resource allocator, and while here, assign the parallel port DRQ, hardware monitor IRQ and drop NIC MAC address on SMBus EEPROM hint, the ms7135 doesn't have such hardware. Signed-off-by: Jonathan A. Kollasch Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/msi/ms7135/Kconfig | 4 ++-- src/mainboard/msi/ms7135/devicetree.cb | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index 8cd1f6d4bc..1123df727f 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -109,10 +109,10 @@ config IRQ_SLOT_COUNT config DCACHE_RAM_BASE hex - default 0xcf000 + default 0xc8000 depends on BOARD_MSI_MS7135 config DCACHE_RAM_SIZE hex - default 0x1000 + default 0x8000 depends on BOARD_MSI_MS7135 diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb index d11bd9e2df..ac686db4d3 100644 --- a/src/mainboard/msi/ms7135/devicetree.cb +++ b/src/mainboard/msi/ms7135/devicetree.cb @@ -21,6 +21,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pnp 4e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 3 end device pnp 4e.2 on # Com1 io 0x60 = 0x3f8 @@ -36,13 +37,14 @@ chip northbridge/amd/amdk8/root_complex # Root complex irq 0x70 = 1 irq 0x72 = 12 end + device pnp 4e.6 off end # XXX keep allocator happy device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5 device pnp 4e.8 off end # GPIO 2 device pnp 4e.9 off end # GPIO 3, GPIO 4 device pnp 4e.a off end # ACPI device pnp 4e.b on # Hardware monitor io 0x60 = 0x290 - irq 0x70 = 0 + irq 0x70 = 5 end end end @@ -64,8 +66,6 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" end end device pci 18.1 on end -- cgit v1.2.3