From 00b81adfedd0f61beb3fd7f3775f5d215b6307c4 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Tue, 13 Feb 2024 20:44:52 +0000 Subject: soc/intel/alderlake: Include ADL-N ID 5 0x4618 This patch adds support for using ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/mainboard/intel/adlrvp/ramstage.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard') diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 3ffc35be95..7a6bb5d04c 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -25,6 +25,7 @@ const struct cpu_power_limits limits[] = { { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, { PCI_DID_INTEL_ADL_N_ID_4, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, 3000, 6000, 25000, 25000, 78000 }, }; WEAK_DEV_PTR(dptf_policy); -- cgit v1.2.3