From 64b53d66dfcbe32a2973dd6d06f0031a4e4e60fd Mon Sep 17 00:00:00 2001 From: Lubomir Rintel Date: Sun, 8 Jan 2017 09:50:30 +0100 Subject: mainboard/winnet/g170: Copy from mainboard/bcom/winnetp680 G170 is a board manufactured by WinNET, used in thin clients including HP Neoware CA19 and IGEL 2110. Copied from mainboard/bcom/winnetp680 which seems to be a similar board with an extra PCI slot. The p680 should probably be moved to winnet/ too, since the board is an OEM WinNET board, with BCom being just a machine that happens to it. Change-Id: I90b89ee634d90cfba2e56cca5b76cfd2bd7a8d0b Signed-off-by: Lubomir Rintel Reviewed-on: https://review.coreboot.org/18898 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/mainboard/winnet/g170/devicetree.cb | 64 +++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 src/mainboard/winnet/g170/devicetree.cb (limited to 'src/mainboard/winnet/g170/devicetree.cb') diff --git a/src/mainboard/winnet/g170/devicetree.cb b/src/mainboard/winnet/g170/devicetree.cb new file mode 100644 index 0000000000..f0a086b642 --- /dev/null +++ b/src/mainboard/winnet/g170/devicetree.cb @@ -0,0 +1,64 @@ +chip northbridge/via/cn700 # Northbridge + device domain 0 on # PCI domain + device pci 0.0 on end # AGP Bridge + device pci 0.1 on end # Error Reporting + device pci 0.2 on end # Host Bus Control + device pci 0.3 on end # Memory Controller + device pci 0.4 on end # Power Management + device pci 0.7 on end # V-Link Controller + device pci 1.0 on end # PCI Bridge + chip southbridge/via/vt8237r # Southbridge + # Enable both IDE channels. + register "ide0_enable" = "1" + register "ide1_enable" = "1" + # Both cables are 40pin. + register "ide0_80pin_cable" = "0" + register "ide1_80pin_cable" = "0" + register "fn_ctrl_lo" = "0x80" + register "fn_ctrl_hi" = "0x1d" + device pci f.0 on end # IDE + device pci 10.0 on end # UHCI + device pci 10.1 on end # UHCI + device pci 10.2 on end # UHCI + device pci 10.3 on end # UHCI + device pci 10.4 on end # EHCI + device pci 11.0 on # Southbridge LPC + chip superio/winbond/w83697hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, GPIO 1 + device pnp 2e.8 off end # MIDI port, GPIO 5 + device pnp 2e.9 off end # GPIO 2-4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + end + end + device pci 11.5 on end # AC'97 audio + device pci 12.0 on end # Ethernet + end + end + device cpu_cluster 0 on # APIC cluster + chip cpu/via/c7 # VIA C7 + device lapic 0 on end # APIC + end + end +end -- cgit v1.2.3