From c18170b241c2b242335e8c2d7bbfdbc138133cc1 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 30 Sep 2003 23:53:45 +0000 Subject: more fixes for via ... plus a little more spew. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/via/epia/auto.c | 26 ++++++++++++++++++++++++++ src/mainboard/via/epia/irq_tables.c | 25 ++++++++++++++++--------- 2 files changed, 42 insertions(+), 9 deletions(-) (limited to 'src/mainboard/via') diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c index e5ea66cec1..fe999b0608 100644 --- a/src/mainboard/via/epia/auto.c +++ b/src/mainboard/via/epia/auto.c @@ -50,6 +50,30 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "sdram/generic_sdram.c" */ +static void +enable_mainboard_devices(void) { + device_t dev; + /* dev 0 for southbridge */ + + dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); + + if (dev == PCI_DEV_INVALID) { + die("Southbridge not found!!!\n"); + } + pci_write_config8(dev, 0x50, 7); + pci_write_config8(dev, 0x51, 0xff); +} + +static void +enable_shadow_ram(void) { + device_t dev = 0; /* no need to look up 0:0.0 */ + unsigned char shadowreg; + /* dev 0 for southbridge */ + shadowreg = pci_read_config8(dev, 0x63); + /* 0xf0000-0xfffff */ + shadowreg |= 0x30; + pci_write_config8(dev, 0x63, shadowreg); +} static void main(void) { unsigned long x; @@ -57,10 +81,12 @@ static void main(void) outb(5, 0x80); enable_vt8231_serial(); + enable_mainboard_devices(); uart_init(); console_init(); enable_smbus(); + enable_shadow_ram(); /* memreset_setup(); this is way more generic than we need. diff --git a/src/mainboard/via/epia/irq_tables.c b/src/mainboard/via/epia/irq_tables.c index b59ce9f1e9..894c27dec5 100644 --- a/src/mainboard/via/epia/irq_tables.c +++ b/src/mainboard/via/epia/irq_tables.c @@ -7,19 +7,26 @@ #include - const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32+16*18, /* there can be total 18 devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - 0x23, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x0, /* Vendor */ - 0x0, /* Device */ - 0, /* Crap (miniport) */ + 32+16*5, /* there can be total 5 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x88, /* Where the interrupt router lies (dev) */ + 0x1c20, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x8231, /* Device */ + 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { + /* 8231 ethernet */ + {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0}, + /* 8231 internal */ + {0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, + /* PCI slot */ + {0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0}, + {0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}, + {0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0}, } }; -- cgit v1.2.3