From 314e551447f408300e56cd6206af3e52d9b22059 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 9 Apr 2010 20:36:29 +0000 Subject: This patch changes C7 CAR code to be a single assembler file instead of the ugly mixture it was before. It also enables CAR for all C7 boards Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/via/epia-cn/Kconfig | 11 ---- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m700/Kconfig | 11 ---- src/mainboard/via/epia-m700/romstage.c | 105 +-------------------------------- src/mainboard/via/pc2500e/Kconfig | 11 ---- src/mainboard/via/pc2500e/romstage.c | 2 +- src/mainboard/via/vt8454c/Kconfig | 11 ---- src/mainboard/via/vt8454c/romstage.c | 16 +---- 8 files changed, 4 insertions(+), 165 deletions(-) (limited to 'src/mainboard/via') diff --git a/src/mainboard/via/epia-cn/Kconfig b/src/mainboard/via/epia-cn/Kconfig index be824330d9..4e50133e5e 100644 --- a/src/mainboard/via/epia-cn/Kconfig +++ b/src/mainboard/via/epia-cn/Kconfig @@ -5,7 +5,6 @@ config BOARD_VIA_EPIA_CN select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_VIA_VT1211 - select ROMCC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 @@ -14,16 +13,6 @@ config MAINBOARD_DIR default via/epia-cn depends on BOARD_VIA_EPIA_CN -#config DCACHE_RAM_BASE -# hex -# default 0xffef0000 -# depends on BOARD_VIA_EPIA_CN -# -#config DCACHE_RAM_SIZE -# hex -# default 0x8000 -# depends on BOARD_VIA_EPIA_CN - config MAINBOARD_PART_NUMBER string default "EPIA-CN" diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index c68c753dad..5fbf84337e 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -86,7 +86,7 @@ static const struct mem_controller ctrl = { .channel0 = { 0x50 }, }; -static void main(unsigned long bist) +void main(unsigned long bist) { unsigned long x; device_t dev; diff --git a/src/mainboard/via/epia-m700/Kconfig b/src/mainboard/via/epia-m700/Kconfig index fe3b799eb3..91bb11ccc5 100644 --- a/src/mainboard/via/epia-m700/Kconfig +++ b/src/mainboard/via/epia-m700/Kconfig @@ -7,23 +7,12 @@ config BOARD_VIA_EPIA_M700 select BOARD_HAS_FADT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 - select USE_PRINTK_IN_CAR config MAINBOARD_DIR string default via/epia-m700 depends on BOARD_VIA_EPIA_M700 -config DCACHE_RAM_BASE - hex - default 0xffef0000 - depends on BOARD_VIA_EPIA_M700 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - depends on BOARD_VIA_EPIA_M700 - config MAINBOARD_PART_NUMBER string default "EPIA-M700" diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index d10e5d16cf..6f8a1c09da 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -381,7 +381,7 @@ void EmbedComInit(void) } /* cache_as_ram.inc jumps to here. */ -void stage1_main(unsigned long bist) +void main(unsigned long bist) { unsigned cpu_reset = 0; u16 boot_mode; @@ -686,108 +686,5 @@ void stage1_main(unsigned long bist) #endif -/* - * The following code is copied from tyan\s2735\romstage.c. - * Only the code around CLEAR_FIRST_1M_RAM is changed. Removed all the code - * around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c". - * The CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop - * at somewhere, and cpu/x86/car/cache_as_ram_post.c do not cache my - * $CONFIG_XIP_ROM_BASE+SIZE area. - * - * Use #include "cpu/via/car/cache_as_ram_post.c". This version post.c have - * some diff with x86-version. - */ -#if 1 - { - /* - * Check value of esp to verify if we have enough ROM for - * stack in Cache as RAM. - */ - unsigned v_esp; - __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)); -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); -#else - print_debug("v_esp="); - print_debug_hex32(v_esp); - print_debug("\n"); -#endif - } -#endif - -#if 1 -cpu_reset_x: - - /* It seems that cpu_reset is not used before this, so I just reset - * it, (this is because the s3 resume, setting in MTRR and copy data - * may destroy stack. - */ - cpu_reset = 0; - -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset); -#else - print_debug("cpu_reset = "); - print_debug_hex32(cpu_reset); - print_debug("\n"); -#endif - - if (cpu_reset == 0) - print_debug("Clearing initial memory region: "); - print_debug("No cache as ram now - "); - - /* Store cpu_reset to ebx. */ - __asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset)); - - /* - * Cancel these lines, CLEAR_FIRST_1M_RAM cause the - * cpu/x86/car/cache_as_ram_post.c stop at somewhere. - */ -#if 0 - if (cpu_reset == 0) { -#define CLEAR_FIRST_1M_RAM 1 -#include "cpu/via/car/cache_as_ram_post.c" - } else { -#undef CLEAR_FIRST_1M_RAM -#include "cpu/via/car/cache_as_ram_post.c" - } -#endif - -#include "cpu/via/car/cache_as_ram_post.c" -/* #include "cpu/x86/car/cache_as_ram_post.c" */ - __asm__ volatile ( - /* Set new esp *//* before CONFIG_RAMBASE */ - "subl %0, %%ebp\n\t" - "subl %0, %%esp\n\t":: - "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_RAMBASE) - ); - - { - unsigned new_cpu_reset; - - /* Get back cpu_reset from ebx. */ - __asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset)); - - /* We can't go back anymore, we lost old stack data in CAR. */ - if (new_cpu_reset == 0) - print_debug("Use Ram as Stack now - done\n"); - else - print_debug("Use Ram as Stack now - \n"); - -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); -#else - print_debug("new_cpu_reset = "); - print_debug_hex32(new_cpu_reset); - print_debug("\n"); -#endif - - /* Copy and execute coreboot_ram. */ - copy_and_run(new_cpu_reset); - /* We will not return. */ - } -#endif - - print_debug("should not be here -\n"); } diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig index 90afe97bf1..a23ec454cd 100644 --- a/src/mainboard/via/pc2500e/Kconfig +++ b/src/mainboard/via/pc2500e/Kconfig @@ -5,7 +5,6 @@ config BOARD_VIA_PC2500E select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_ITE_IT8716F - select ROMCC select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP @@ -22,16 +21,6 @@ config MAINBOARD_PART_NUMBER default "pc2500e" depends on BOARD_VIA_PC2500E -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on BOARD_VIA_PC2500E - -config DCACHE_RAM_SIZE - hex - default 0x1000 - depends on BOARD_VIA_PC2500E - config RAMBASE hex default 0x4000 diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 71ad25908a..c0b34ab153 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -58,7 +58,7 @@ static const struct mem_controller ctrl = { .channel0 = { 0x50 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; -static void main(unsigned long bist) +void main(unsigned long bist) { /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index eec8195fb1..f575e8098f 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -8,7 +8,6 @@ config BOARD_VIA_VT8454C select HAVE_PIRQ_TABLE select HAVE_MP_TABLE # select MMCONF_SUPPORT - select USE_PRINTK_IN_CAR select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 @@ -19,16 +18,6 @@ config MAINBOARD_DIR default via/vt8454c depends on BOARD_VIA_VT8454C -config DCACHE_RAM_BASE - hex - default 0xffef0000 - depends on BOARD_VIA_VT8454C - -config DCACHE_RAM_SIZE - hex - default 0x8000 - depends on BOARD_VIA_VT8454C - config MAINBOARD_PART_NUMBER string default "VT8454c" diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index f7815bb305..dea85bc234 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -32,8 +32,6 @@ #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/bist.h" -#define DEACTIVATE_CAR 1 -#define DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c" #include "pc80/udelay_io.c" #include "lib/delay.c" @@ -89,7 +87,7 @@ static void enable_shadow_ram(const struct mem_controller *ctrl) pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); } -static void main(unsigned long bist) +void main(unsigned long bist) { /* Set statically so it should work with cx700 as well */ static const struct mem_controller cx700[] = { @@ -115,17 +113,5 @@ static void main(unsigned long bist) sdram_set_registers(cx700); enable_shadow_ram(cx700); sdram_enable(cx700); - -#ifdef DEACTIVATE_CAR - print_debug("Deactivating CAR"); -#include DEACTIVATE_CAR_FILE - print_debug(" - Done.\n"); -#endif - copy_and_run(0); -} - -void stage1_main(unsigned long bist) -{ - main(bist); } -- cgit v1.2.3