From 38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 8 Feb 2010 12:20:50 +0000 Subject: janitor task: unify and cleanup naming. cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/via/vt8454c/Makefile.inc | 6 +- src/mainboard/via/vt8454c/auto.c | 134 --------------------------------- src/mainboard/via/vt8454c/romstage.c | 134 +++++++++++++++++++++++++++++++++ 3 files changed, 137 insertions(+), 137 deletions(-) delete mode 100644 src/mainboard/via/vt8454c/auto.c create mode 100644 src/mainboard/via/vt8454c/romstage.c (limited to 'src/mainboard/via/vt8454c') diff --git a/src/mainboard/via/vt8454c/Makefile.inc b/src/mainboard/via/vt8454c/Makefile.inc index 09de4d1232..8f321c2e4b 100644 --- a/src/mainboard/via/vt8454c/Makefile.inc +++ b/src/mainboard/via/vt8454c/Makefile.inc @@ -32,7 +32,7 @@ crt0s += $(src)/cpu/x86/32bit/entry32.inc crt0s += $(src)/cpu/x86/16bit/reset16.inc crt0s += $(src)/arch/i386/lib/id.inc crt0s += $(src)/cpu/via/car/cache_as_ram.inc -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb ldscripts += $(src)/cpu/x86/16bit/entry16.lds @@ -49,8 +49,8 @@ $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.d $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@ perl -e 's/\.rodata/.rom.data/g' -pi $@ perl -e 's/\.text/.section .rom.text/g' -pi $@ diff --git a/src/mainboard/via/vt8454c/auto.c b/src/mainboard/via/vt8454c/auto.c deleted file mode 100644 index e2065095c1..0000000000 --- a/src/mainboard/via/vt8454c/auto.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#include -#include -#include -#include -#include -#include -#include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -#include "northbridge/via/cx700/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" - -#define DEACTIVATE_CAR 1 -#define DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c" -#include "cpu/x86/car/copy_and_run.c" -#include "pc80/udelay_io.c" -#include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/via/cx700/cx700_early_smbus.c" -#include "debug.c" - -#include "northbridge/via/cx700/cx700_early_serial.c" -#include "northbridge/via/cx700/raminit.c" - -static void enable_mainboard_devices(void) -{ - device_t dev; - - dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0); - if (dev == PCI_DEV_INVALID) { - die("LPC bridge not found!!!\n"); - } - // Disable GP3 - pci_write_config8(dev, 0x98, 0x00); - - // Disable mc97 - pci_write_config8(dev, 0x50, 0x80); - - // Disable internal KBC Configuration - pci_write_config8(dev, 0x51, 0x2d); - pci_write_config8(dev, 0x58, 0x42); - pci_write_config8(dev, 0x59, 0x80); - pci_write_config8(dev, 0x5b, 0x01); - - // Enable P2P Bridge Header for External PCI BUS. - dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0); - if (dev == PCI_DEV_INVALID) { - die("P2P bridge not found!!!\n"); - } - pci_write_config8(dev, 0x4f, 0x41); - - // Switch SATA to non-RAID mode - dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0); - if (dev != PCI_DEV_INVALID) { - pci_write_config16(dev, 0xBA, 0x5324); - } -} - -static void enable_shadow_ram(const struct mem_controller *ctrl) -{ - u8 shadowreg; - - pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a); - - /* 0xf0000-0xfffff - ACPI tables */ - shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); - shadowreg |= 0x30; - pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); -} - -static void main(unsigned long bist) -{ - /* Set statically so it should work with cx700 as well */ - static const struct mem_controller cx700[] = { - { - .channel0 = {0x50, 0x51}, - }, - }; - - enable_smbus(); - - enable_cx700_serial(); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - enable_mainboard_devices(); - - /* Allows access to all northbridge devices */ - pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); - - sdram_set_registers(cx700); - enable_shadow_ram(cx700); - sdram_enable(cx700); - -#ifdef DEACTIVATE_CAR - print_debug("Deactivating CAR"); -#include DEACTIVATE_CAR_FILE - print_debug(" - Done.\r\n"); -#endif - copy_and_run(0); -} - -void amd64_main(unsigned long bist) { - main(bist); -} diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c new file mode 100644 index 0000000000..e2065095c1 --- /dev/null +++ b/src/mainboard/via/vt8454c/romstage.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include +#include +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "northbridge/via/cx700/raminit.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" + +#define DEACTIVATE_CAR 1 +#define DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c" +#include "cpu/x86/car/copy_and_run.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/via/cx700/cx700_early_smbus.c" +#include "debug.c" + +#include "northbridge/via/cx700/cx700_early_serial.c" +#include "northbridge/via/cx700/raminit.c" + +static void enable_mainboard_devices(void) +{ + device_t dev; + + dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0); + if (dev == PCI_DEV_INVALID) { + die("LPC bridge not found!!!\n"); + } + // Disable GP3 + pci_write_config8(dev, 0x98, 0x00); + + // Disable mc97 + pci_write_config8(dev, 0x50, 0x80); + + // Disable internal KBC Configuration + pci_write_config8(dev, 0x51, 0x2d); + pci_write_config8(dev, 0x58, 0x42); + pci_write_config8(dev, 0x59, 0x80); + pci_write_config8(dev, 0x5b, 0x01); + + // Enable P2P Bridge Header for External PCI BUS. + dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0); + if (dev == PCI_DEV_INVALID) { + die("P2P bridge not found!!!\n"); + } + pci_write_config8(dev, 0x4f, 0x41); + + // Switch SATA to non-RAID mode + dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0); + if (dev != PCI_DEV_INVALID) { + pci_write_config16(dev, 0xBA, 0x5324); + } +} + +static void enable_shadow_ram(const struct mem_controller *ctrl) +{ + u8 shadowreg; + + pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a); + + /* 0xf0000-0xfffff - ACPI tables */ + shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); + shadowreg |= 0x30; + pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); +} + +static void main(unsigned long bist) +{ + /* Set statically so it should work with cx700 as well */ + static const struct mem_controller cx700[] = { + { + .channel0 = {0x50, 0x51}, + }, + }; + + enable_smbus(); + + enable_cx700_serial(); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + enable_mainboard_devices(); + + /* Allows access to all northbridge devices */ + pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); + + sdram_set_registers(cx700); + enable_shadow_ram(cx700); + sdram_enable(cx700); + +#ifdef DEACTIVATE_CAR + print_debug("Deactivating CAR"); +#include DEACTIVATE_CAR_FILE + print_debug(" - Done.\r\n"); +#endif + copy_and_run(0); +} + +void amd64_main(unsigned long bist) { + main(bist); +} -- cgit v1.2.3