From bb65180ee8b2cb26ac75fe6ccc9525ecc060c1e3 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Wed, 26 Feb 2020 12:39:09 +0300 Subject: mb/up/squared: move USB config to device tree Change-Id: Ic4db37112e7b2329f9e4885139deca12557ffe3a Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39134 Reviewed-by: Felix Singer Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/up/squared/devicetree.cb | 14 ++++++++++++++ src/mainboard/up/squared/ramstage.c | 10 ---------- 2 files changed, 14 insertions(+), 10 deletions(-) (limited to 'src/mainboard/up/squared') diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 66be75cc05..d7281a6cd8 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -1,5 +1,19 @@ chip soc/intel/apollolake + # Override USB port configuration + register "usb_config_override" = "1" + # USB 2.0 + register "usb2_port[0]" = "PORT_EN(OC0)" + register "usb2_port[1]" = "PORT_EN(OC1)" + register "usb2_port[2]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC1)" + register "usb2_port[4]" = "PORT_EN(OC1)" + register "usb2_port[5]" = "PORT_EN(OC1)" + register "usb2_port[6]" = "PORT_EN(OC_SKIP)" + register "usb2_port[7]" = "PORT_EN(OC_SKIP)" + # USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + register "enable_vtd" = "1" device cpu_cluster 0 on diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index 637b8d87c9..9ae30ebb16 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -80,14 +80,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; // 0x1 silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; // 0x0 silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; // 0x0 - - silconfig->PortUs30bOverCurrentPin[0] = 0x0; // 0x1 - - silconfig->PortUs20bOverCurrentPin[1] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[2] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[3] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[4] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[5] = 0x1; // 0x0 - silconfig->PortUs20bOverCurrentPin[6] = 0x2; // 0x0 - silconfig->PortUs20bOverCurrentPin[7] = 0x2; // 0x0 } -- cgit v1.2.3