From 8376831eafc1be1175529fd21e0d2fe40339d4eb Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Tue, 6 Jul 2010 20:36:36 +0000 Subject: A bug fix: Fix the ctrl_devport_conf_clear to clear the enable bit. A simplification: Dynamically enable ck804s that are found instead of relying on #defines. Removing an Opteron changes the number of ck804s that are present. Simple changes to make it easier to compare the factory BIOS with Coreboot when using SerialICE for boards with the Nvidia ck804 chipset: If the mask is zero, don't read the value, just write the new value over it. Signed-off-by: Myles Watson Acked-by: Myles Watson git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/tyan/s2892/romstage.c | 1 - src/mainboard/tyan/s2895/romstage.c | 2 -- 2 files changed, 3 deletions(-) (limited to 'src/mainboard/tyan') diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index b84d6b6057..cef89942a5 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -60,7 +60,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define CK804_NUM 1 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode #define CK804_MB_SETUP \ diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 60f348ce23..486aa8d95a 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -73,7 +73,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" -#define CK804_NUM 2 #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 @@ -90,7 +89,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/ck804/ck804_early_setup_car.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -- cgit v1.2.3