From 59e03342076ea79cb7c0ed2fdbd199947c8c5212 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 20 Nov 2016 11:03:13 +0200 Subject: AGESA: Switch to MMCONF_SUPPORT_DEFAULT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/tyan/s8226/Kconfig | 1 - src/mainboard/tyan/s8226/romstage.c | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/tyan') diff --git a/src/mainboard/tyan/s8226/Kconfig b/src/mainboard/tyan/s8226/Kconfig index 733f1c44e3..46107580c2 100644 --- a/src/mainboard/tyan/s8226/Kconfig +++ b/src/mainboard/tyan/s8226/Kconfig @@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict config MAINBOARD_DIR string diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 7460f208ce..d43c04b4cc 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -38,8 +38,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - post_code(0x30); + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); + post_code(0x31); /* For serial port. */ -- cgit v1.2.3