From 14e22779625de673569c7b950ecc2753fb915b31 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 27 Apr 2010 06:56:47 +0000 Subject: Since some people disapprove of white space cleanups mixed in regular commits while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/tyan/s4880/devicetree.cb | 8 ++++---- src/mainboard/tyan/s4880/irq_tables.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 26 +++++++++++++------------- src/mainboard/tyan/s4880/resourcemap.c | 6 +++--- src/mainboard/tyan/s4880/romstage.c | 8 ++++---- 5 files changed, 25 insertions(+), 25 deletions(-) (limited to 'src/mainboard/tyan/s4880') diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb index 4a08e45d1b..4c2f2b59f4 100644 --- a/src/mainboard/tyan/s4880/devicetree.cb +++ b/src/mainboard/tyan/s4880/devicetree.cb @@ -9,7 +9,7 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end # LDT0 device pci 18.0 on end # LDT1 - device pci 18.0 on # northbridge + device pci 18.0 on # northbridge # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory @@ -68,7 +68,7 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI @@ -86,8 +86,8 @@ chip northbridge/amd/amdk8/root_complex register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 - + end # device pci 18.0 + device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end diff --git a/src/mainboard/tyan/s4880/irq_tables.c b/src/mainboard/tyan/s4880/irq_tables.c index e95038dc37..352a7411e1 100644 --- a/src/mainboard/tyan/s4880/irq_tables.c +++ b/src/mainboard/tyan/s4880/irq_tables.c @@ -1,4 +1,4 @@ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index 746d2a5d5e..a5094ba042 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -28,7 +28,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) dst_node = (config_map >> 4) & 7; dst_link = (config_map >> 8) & 3; bus_base = (config_map >> 16) & 0xff; -#if 0 +#if 0 printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", dst_node, dst_link, bus_base, reg, config_map); @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) unsigned apicid_8111; unsigned apicid_8131_1; unsigned apicid_8131_2; - + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -78,7 +78,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); - + { device_t dev; @@ -88,14 +88,14 @@ static void *smp_write_config_table(void *v) printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); bus_chain_0 = 1; } - + /* 8111 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } + bus_isa++; + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -133,14 +133,14 @@ static void *smp_write_config_table(void *v) } smp_write_bus(mc, bus_isa, "ISA "); - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; @@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v) } } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1); @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13); @@ -214,7 +214,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// -//Slot 3 PCIX 100/66 +//Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// diff --git a/src/mainboard/tyan/s4880/resourcemap.c b/src/mainboard/tyan/s4880/resourcemap.c index cf45d55532..5fa85784ab 100644 --- a/src/mainboard/tyan/s4880/resourcemap.c +++ b/src/mainboard/tyan/s4880/resourcemap.c @@ -144,7 +144,7 @@ static void setup_s4880_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -200,7 +200,7 @@ static void setup_s4880_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -208,7 +208,7 @@ static void setup_s4880_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 9933303278..753328c062 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -1,4 +1,4 @@ - + #include #include #include @@ -65,7 +65,7 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x01, device); print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); @@ -85,7 +85,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" /* tyan does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 @@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_s4880_resource_map(); needs_reset = setup_coherent_ht_domain(); - + #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); -- cgit v1.2.3