From ef03afa405b049a172146aab93cfb81fb21f3945 Mon Sep 17 00:00:00 2001 From: "arch import user (historical)" Date: Wed, 6 Jul 2005 17:15:30 +0000 Subject: Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34 Creator: Yinghai Lu AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/tyan/s2895/Config.lb | 10 +++++++ src/mainboard/tyan/s2895/Options.lb | 10 ++++++- src/mainboard/tyan/s2895/auto.c | 52 ++++++++++++++++++++++++++++++++++--- src/mainboard/tyan/s2895/failover.c | 18 ++++++++++++- src/mainboard/tyan/s2895/mptable.c | 22 +++++++++++----- 5 files changed, 100 insertions(+), 12 deletions(-) (limited to 'src/mainboard/tyan/s2895') diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb index 5a7cb14e9a..09448facc8 100644 --- a/src/mainboard/tyan/s2895/Config.lb +++ b/src/mainboard/tyan/s2895/Config.lb @@ -315,4 +315,14 @@ chip northbridge/amd/amdk8/root_complex end end # PCI domain +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 off end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 on end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end end #root_complex diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index 545dbe9f42..22812e9a20 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -9,6 +9,8 @@ uses HARD_RESET_FUNCTION uses IRQ_SLOT_COUNT uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS +uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP uses FALLBACK_SIZE @@ -53,6 +55,7 @@ uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN +uses K8_E0_MEM_HOLE_SIZEK uses CK804_DEVN_BASE @@ -115,11 +118,16 @@ default LB_CKS_LOC=123 ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_CPUS=4 +default CONFIG_MAX_PHYSICAL_CPUS=2 +default CONFIG_LOGICAL_CPUS=1 #CHIP_NAME ? #default CONFIG_CHIP_NAME=1 +#1G memory hole +default K8_E0_MEM_HOLE_SIZEK=0x100000 + #CK804 setting default CK804_DEVN_BASE=0 diff --git a/src/mainboard/tyan/s2895/auto.c b/src/mainboard/tyan/s2895/auto.c index 209f284d58..b6f121e6e8 100644 --- a/src/mainboard/tyan/s2895/auto.c +++ b/src/mainboard/tyan/s2895/auto.c @@ -105,6 +105,13 @@ static inline int spd_read_byte(unsigned device, unsigned address) /* tyan does not want the default */ #include "resourcemap.c" +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#include "cpu/amd/dualcore/dualcore.c" +#else +#include "cpu/amd/model_fxx/node_id.c" +#endif + #define FIRST_CPU 1 #define SECOND_CPU 1 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) @@ -113,6 +120,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define CK804B_BUSN 0xc #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 +#include "southbridge/nvidia/ck804/ck804_early_setup.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode @@ -155,26 +163,57 @@ static void main(unsigned long bist) }; int needs_reset; +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else unsigned nodeid; +#endif if (bist == 0) { /* Skip this if there was a built in self test failure */ amd_early_mtrr_init(); - nodeid = lapicid();; +#if CONFIG_LOGICAL_CPUS==1 + set_apicid_cpuid_lo(); + + id = get_node_core_id_x(); // that is initid + #if ENABLE_APIC_EXT_ID == 1 + if(id.coreid == 0) { + enable_apic_ext_id(id.nodeid); + } + #endif +#else + nodeid = get_node_id(); #if ENABLE_APIC_EXT_ID == 1 enable_apic_ext_id(nodeid); #endif +#endif enable_lapic(); init_timer(); +#if CONFIG_LOGICAL_CPUS==1 + #if ENABLE_APIC_EXT_ID == 1 + #if LIFT_BSP_APIC_ID == 0 + if( id.nodeid != 0 ) + #endif + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); + #endif + + if(id.coreid == 0) { + if (cpu_init_detected(id.nodeid)) { + asm volatile ("jmp __cpu_reset"); + } + distinguish_cpu_resets(id.nodeid); + } + +#else #if ENABLE_APIC_EXT_ID == 1 #if LIFT_BSP_APIC_ID == 0 if(nodeid != 0) #endif - lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10 + lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); #endif @@ -182,11 +221,15 @@ static void main(unsigned long bist) asm volatile ("jmp __cpu_reset"); } distinguish_cpu_resets(nodeid); +#endif if (!boot_cpu() +#if CONFIG_LOGICAL_CPUS==1 + || (id.coreid != 0) +#endif ) { - stop_this_cpu(); // it will stop all cores except core0 of cpu0 + stop_this_cpu(); } } @@ -203,6 +246,9 @@ static void main(unsigned long bist) setup_s2895_resource_map(); needs_reset = setup_coherent_ht_domain(); +#if CONFIG_LOGICAL_CPUS==1 + start_other_cores(); +#endif needs_reset |= ht_setup_chains_x(); diff --git a/src/mainboard/tyan/s2895/failover.c b/src/mainboard/tyan/s2895/failover.c index a70264ec2f..7cd004f82b 100644 --- a/src/mainboard/tyan/s2895/failover.c +++ b/src/mainboard/tyan/s2895/failover.c @@ -50,16 +50,32 @@ static void sio_setup(void) } +#if CONFIG_LOGICAL_CPUS==1 +#include "cpu/amd/dualcore/dualcore_id.c" +#else +#include "cpu/amd/model_fxx/node_id.c" +#endif + static unsigned long main(unsigned long bist) { +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else unsigned nodeid; +#endif /* Make cerain my local apic is useable */ // enable_lapic(); - nodeid = lapicid();; +#if CONFIG_LOGICAL_CPUS==1 + id = get_node_core_id_x(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(id.nodeid)) { +#else + nodeid = get_node_id(); /* Is this a cpu only reset? */ if (cpu_init_detected(nodeid)) { +#endif if (last_boot_normal()) { goto normal_image; } else { diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index 61ab3f26a8..f6b534d866 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -4,6 +4,10 @@ #include #include +#if CONFIG_LOGICAL_CPUS==1 +#include +#endif + void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; @@ -142,7 +146,11 @@ void *smp_write_config_table(void *v) smp_write_bus(mc, bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ - apicid_base = CONFIG_MAX_CPUS; +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(4); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif apicid_ck804 = apicid_base; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; @@ -163,10 +171,10 @@ void *smp_write_config_table(void *v) dword = 0x0120d218; pci_write_config32(dev, 0x7c, dword); - dword = 0x00001a00; + dword = 0x12008a00; pci_write_config32(dev, 0x80, dword); - dword = 0x00080d72; + dword = 0x00080d7d; pci_write_config32(dev, 0x84, dword); } @@ -222,15 +230,15 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+4)<<2)|0, apicid_ck804, 0x14); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +0x0a)<<2)|0, apicid_ck804, 0x15); -- cgit v1.2.3