From 13f1c2af8be2cd7f7e99a678f5d428a65b771811 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Fri, 8 Jul 2005 02:49:49 +0000 Subject: eric patch 1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/tyan/s2892/auto.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mainboard/tyan/s2892/auto.c') diff --git a/src/mainboard/tyan/s2892/auto.c b/src/mainboard/tyan/s2892/auto.c index d2512e9f61..25967056de 100644 --- a/src/mainboard/tyan/s2892/auto.c +++ b/src/mainboard/tyan/s2892/auto.c @@ -142,7 +142,6 @@ static void main(unsigned long bist) enable_lapic(); init_timer(); - #if CONFIG_LOGICAL_CPUS==1 id = get_node_core_id_x(); if(id.coreid == 0) { @@ -150,6 +149,7 @@ static void main(unsigned long bist) asm volatile ("jmp __cpu_reset"); } distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); } #else nodeid = lapicid(); @@ -164,7 +164,7 @@ static void main(unsigned long bist) || (id.coreid != 0) #endif ) { - stop_this_cpu(); + stop_this_cpu(); // it will stop all cores except core0 of cpu0 } } @@ -174,13 +174,14 @@ static void main(unsigned long bist) console_init(); /* Halt if there was a built in self test failure */ - report_bist_failure(bist); +// report_bist_failure(bist); setup_s2892_resource_map(); needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif needs_reset |= ht_setup_chains_x(); -- cgit v1.2.3