From 806e146e754a44f96c693cde707065b14f80d8a2 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 1 Dec 2005 10:54:44 +0000 Subject: Applying 11_26_car_tyan.diff from Yinghai Lu. NOTE: This will break the tree so it can be fixed up later git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/tyan/s2891/Config.lb | 102 +++++----- src/mainboard/tyan/s2891/Options.lb | 34 +++- src/mainboard/tyan/s2891/cache_as_ram_auto.c | 267 ++++++--------------------- 3 files changed, 133 insertions(+), 270 deletions(-) (limited to 'src/mainboard/tyan/s2891') diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb index 6341926115..7dd9bee1bc 100644 --- a/src/mainboard/tyan/s2891/Config.lb +++ b/src/mainboard/tyan/s2891/Config.lb @@ -97,9 +97,13 @@ end ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/x86/16bit/entry16.inc +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds + if USE_DCACHE_RAM if CONFIG_USE_INIT @@ -213,7 +217,7 @@ chip northbridge/amd/amdk8/root_complex device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 @@ -226,11 +230,11 @@ chip northbridge/amd/amdk8/root_complex io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # Com2 + device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 off # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 @@ -247,55 +251,55 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.b off # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end end device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end +# end +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 54 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 55 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 56 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 57 on end +# end end # SM - device pci 1.1 on # SM 1 - chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 - device i2c 2d on end - end - chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 - device i2c 2e on end - end - chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN - device i2c 2a on end - end - chip drivers/generic/generic # Winbond HWM 0x92 - device i2c 49 on end - end - chip drivers/generic/generic # Winbond HWM 0x94 - device i2c 4a on end - end - end #SM +# device pci 1.1 on # SM 1 +# chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 +# device i2c 2d on end +# end +# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 +# device i2c 2e on end +# end +# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN +# device i2c 2a on end +# end +# chip drivers/generic/generic # Winbond HWM 0x92 +# device i2c 49 on end +# end +# chip drivers/generic/generic # Winbond HWM 0x94 +# device i2c 4a on end +# end +# end #SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 off end # ACI @@ -307,8 +311,8 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/ati/ragexl chip drivers/pci/onboard device pci 7.0 on end - register "rom_address" = "0xfff80000" #for 512K - #register "rom_address" = "0xfff00000" #for 1M + # register "rom_address" = "0xfff80000" #for 512K + register "rom_address" = "0xfff00000" #for 1M end end device pci a.0 off end # NIC diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index 80313a1cff..fdb8e7a745 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -53,7 +53,7 @@ uses CONFIG_GDB_STUB uses CONFIG_CHIP_NAME uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses K8_E0_MEM_HOLE_SIZEK +uses K8_HW_MEM_HOLE_SIZEK uses CK804_DEVN_BASE @@ -62,18 +62,26 @@ uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT +uses ENABLE_APIC_EXT_ID +uses APIC_ID_OFFSET +uses LIFT_BSP_APIC_ID + +uses CONFIG_PCI_64BIT_PREF_MEM + ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes -default ROM_SIZE=524288 +#default ROM_SIZE=524288 #1M bytes -#default ROM_SIZE=1048576 +default ROM_SIZE=1048576 ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -default FALLBACK_SIZE=131072 +#default FALLBACK_SIZE=131072 +#256K +default FALLBACK_SIZE=0x40000 ### ### Build options @@ -123,27 +131,33 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_LOGICAL_CPUS=1 #1G memory hole -default K8_E0_MEM_HOLE_SIZEK=0x100000 +default K8_HW_MEM_HOLE_SIZEK=0x100000 #CK804 setting -#default CK804_DEVN_BASE=0 +default CK804_DEVN_BASE=0 #BTEXT Console #default CONFIG_CONSOLE_BTEXT=1 #VGA Console -#default CONFIG_CONSOLE_VGA=1 -#default CONFIG_PCI_ROM_RUN=1 +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=0 +default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 +default CONFIG_USE_INIT=1 + +default ENABLE_APIC_EXT_ID=1 +default APIC_ID_OFFSET=0x10 +default LIFT_BSP_APIC_ID=0 + +#default CONFIG_PCI_64BIT_PREF_MEM=1 ## ## Build code to setup a generic IOAPIC diff --git a/src/mainboard/tyan/s2891/cache_as_ram_auto.c b/src/mainboard/tyan/s2891/cache_as_ram_auto.c index b78a899764..67e63982e4 100644 --- a/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -1,5 +1,13 @@ #define ASSEMBLY 1 #define __ROMCC__ + +//used by raminit +#define K8_4RANK_DIMM_SUPPORT 1 + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif + #include #include @@ -14,8 +22,6 @@ #include "ram/ramtest.c" #include "northbridge/amd/amdk8/cpu_rev.c" -//#define K8_HT_FREQ_1G_SUPPORT 1 -//#define K8_SCAN_PCI_BUS 1 #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" @@ -73,8 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#define K8_4RANK_DIMM_SUPPORT 1 - #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "sdram/generic_sdram.c" @@ -82,16 +86,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) /* tyan does not want the default */ #include "resourcemap.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 #include "cpu/amd/dualcore/dualcore.c" -#else -#include "cpu/amd/model_fxx/node_id.c" -#endif - -#define FIRST_CPU 1 -#define SECOND_CPU 1 -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define CK804_NUM 1 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" @@ -99,6 +94,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + + #if USE_FALLBACK_IMAGE == 1 #include "southbridge/nvidia/ck804/ck804_enable_rom.c" @@ -127,38 +127,14 @@ static void sio_setup(void) #endif } -void real_main(unsigned long bist); -void amd64_main(unsigned long bist) +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) { -#if CONFIG_LOGICAL_CPUS==1 - struct node_core_id id; -#else - unsigned nodeid; -#endif - /* Make cerain my local apic is useable */ -// enable_lapic(); + unsigned last_boot_normal_x = last_boot_normal(); -#if CONFIG_LOGICAL_CPUS==1 - id = get_node_core_id_x(); - /* Is this a cpu only reset? */ - if (cpu_init_detected(id.nodeid)) { -#else -// nodeid = lapicid() & 0xf; - nodeid = get_node_id(); - /* Is this a cpu only reset? */ - if (cpu_init_detected(nodeid)) { -#endif - if (last_boot_normal()) { - goto normal_image; - } else { - goto cpu_reset; - } - } - - /* Is this a secondary cpu? */ - if (!boot_cpu()) { - if (last_boot_normal()) { + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { goto normal_image; } else { goto fallback_image; @@ -176,7 +152,7 @@ void amd64_main(unsigned long bist) ck804_enable_rom(); /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { + if (bios_reset_detected() && last_boot_normal_x) { goto normal_image; } /* This is the primary cpu how should I boot? */ @@ -189,105 +165,48 @@ void amd64_main(unsigned long bist) normal_image: __asm__ volatile ("jmp __normal_image" : /* outputs */ - : "a" (bist) /* inputs */ - ); - cpu_reset: -#if 0 - //CPU reset will reset memtroller ??? - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ + : "a" (bist) , "b" (cpu_init_detectedx)/* inputs */ ); -#endif fallback_image: - real_main(bist); + ; } -void real_main(unsigned long bist) -#else -void amd64_main(unsigned long bist) -#endif -{ - static const struct mem_controller cpu[] = { -#if FIRST_CPU - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }, -#endif -#if SECOND_CPU - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }, #endif - }; - int needs_reset; - unsigned cpu_reset = 0; +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - if (bist == 0) { -#if CONFIG_LOGICAL_CPUS==1 - struct node_core_id id; -#else - unsigned nodeid; -#endif - /* Skip this if there was a built in self test failure */ -// amd_early_mtrr_init(); # don't need, already done in cache_as_ram +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ -#if CONFIG_LOGICAL_CPUS==1 - set_apicid_cpuid_lo(); - id = get_node_core_id_x(); // that is initid -#else - nodeid = get_node_id(); +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); #endif + real_main(bist, cpu_init_detectedx); - enable_lapic(); -// init_timer(); +} -#if CONFIG_LOGICAL_CPUS==1 - if(id.coreid == 0) { - if (cpu_init_detected(id.nodeid)) { - cpu_reset = 1; - goto cpu_reset_x; - } - distinguish_cpu_resets(id.nodeid); -// start_other_core(id.nodeid); - } -#else - if (cpu_init_detected(nodeid)) { - cpu_reset = 1; - goto cpu_reset_x; - } - distinguish_cpu_resets(nodeid); +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr [] = { + (0xa<<3)|0, (0xa<<3)|2, 0, 0, + (0xa<<3)|1, (0xa<<3)|3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + (0xa<<3)|4, (0xa<<3)|6, 0, 0, + (0xa<<3)|5, (0xa<<3)|7, 0, 0, #endif + }; + int needs_reset; + unsigned cpu_reset = 0; + unsigned bsp_apicid = 0; - if (!boot_cpu() -#if CONFIG_LOGICAL_CPUS==1 - || (id.coreid != 0) -#endif - ) { - // We need stop the CACHE as RAM for this CPU too - #include "cpu/amd/car/cache_as_ram_post.c" - stop_this_cpu(); // it will stop all cores except core0 of cpu0 - } + struct mem_controller ctrl[8]; + unsigned nodes; + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx); } - init_timer(); // only do it it first CPU - - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); @@ -301,9 +220,12 @@ void amd64_main(unsigned long bist) #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched + wait_all_core0_started(); start_other_cores(); #endif - // automatically set that for you, but you might meet tight space + + wait_all_aps_started(bsp_apicid); + needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); @@ -313,93 +235,16 @@ void amd64_main(unsigned long bist) soft_reset(); } - enable_smbus(); - - memreset_setup(); - sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - -#if 1 - { - /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ - unsigned v_esp; - __asm__ volatile ( - "movl %%esp, %0\n\t" - : "=a" (v_esp) - ); -#if CONFIG_USE_INIT - printk_debug("v_esp=%08x\r\n", v_esp); -#else - print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); -#endif - } - -#endif -#if 1 - -cpu_reset_x: + allow_all_aps_stop(bsp_apicid); -#if CONFIG_USE_INIT - printk_debug("cpu_reset = %08x\r\n",cpu_reset); -#else - print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); -#endif - - if(cpu_reset == 0) { - print_debug("Clearing initial memory region: "); - } - print_debug("No cache as ram now - "); - - /* store cpu_reset to ebx */ - __asm__ volatile ( - "movl %0, %%ebx\n\t" - ::"a" (cpu_reset) - ); - - if(cpu_reset==0) { -#define CLEAR_FIRST_1M_RAM 1 -#include "cpu/amd/car/cache_as_ram_post.c" - } - else { -#undef CLEAR_FIRST_1M_RAM -#include "cpu/amd/car/cache_as_ram_post.c" - } - - __asm__ volatile ( - /* set new esp */ /* before _RAMBASE */ - "subl %0, %%ebp\n\t" - "subl %0, %%esp\n\t" - ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE ) - ); - - { - unsigned new_cpu_reset; - - /* get back cpu_reset from ebx */ - __asm__ volatile ( - "movl %%ebx, %0\n\t" - :"=a" (new_cpu_reset) - ); - - /* We can not go back any more, we lost old stack data in cache as ram*/ - if(new_cpu_reset==0) { - print_debug("Use Ram as Stack now - done\r\n"); - } else - { - print_debug("Use Ram as Stack now - \r\n"); - } -#if CONFIG_USE_INIT - printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset); -#else - print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); -#endif - - /*copy and execute linuxbios_ram */ - copy_and_run(new_cpu_reset); - /* We will not return */ - } -#endif + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); + enable_smbus(); - print_debug("should not be here -\r\n"); + memreset_setup(); + sdram_initialize(nodes, ctrl); + post_cache_as_ram(cpu_reset); } -- cgit v1.2.3