From 7dec0f9ac33b1053de5045d6d72d6f882e0c782a Mon Sep 17 00:00:00 2001
From: "arch import user (historical)" <svn@openbios.org>
Date: Wed, 6 Jul 2005 18:17:06 +0000
Subject: Revision:
 linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-56 Creator: 
 Yinghai Lu <yhlu@tyan.com>

remove junk in s2885 cache_as_ram_auto.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/mainboard/tyan/s2885/cache_as_ram_auto.c | 54 ----------------------------
 1 file changed, 54 deletions(-)

(limited to 'src/mainboard/tyan/s2885')

diff --git a/src/mainboard/tyan/s2885/cache_as_ram_auto.c b/src/mainboard/tyan/s2885/cache_as_ram_auto.c
index 9ca2c4dc7f..3d27071031 100644
--- a/src/mainboard/tyan/s2885/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2885/cache_as_ram_auto.c
@@ -13,16 +13,6 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 
-#if 0
-static void post_code(uint8_t value) {
-#if 1
-        int i;
-        for(i=0;i<0x80000;i++) {
-                outb(value, 0x80);
-        }
-#endif
-}
-#endif
 
 #include "northbridge/amd/amdk8/cpu_rev.c"
 #define K8_HT_FREQ_1G_SUPPORT 0
@@ -156,7 +146,6 @@ void amd64_main(unsigned long bist)
         }
 
         /* Is this a secondary cpu? */
-//        post_code(0x21);
         if (!boot_cpu()) {
                 if (last_boot_normal()) {
                         goto normal_image;
@@ -170,11 +159,9 @@ void amd64_main(unsigned long bist)
 
         enumerate_ht_chain();
 
-        /* Setup the ck804 */
         amd8111_enable_rom();
 
         /* Is this a deliberate reset by the bios */
-//        post_code(0x22);
         if (bios_reset_detected() && last_boot_normal()) {
                 goto normal_image;
         }
@@ -186,13 +173,11 @@ void amd64_main(unsigned long bist)
                 goto fallback_image;
         }
  normal_image:
-//        post_code(0x23);
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
                 : "a" (bist) /* inputs */
                 );
  cpu_reset:
-//        post_code(0x24);
 #if 0
         //CPU reset will reset memtroller ???
         asm volatile ("jmp __cpu_reset" 
@@ -202,7 +187,6 @@ void amd64_main(unsigned long bist)
 #endif
 
  fallback_image:
-//        post_code(0x25);
         real_main(bist);
 }
 void real_main(unsigned long bist)
@@ -265,7 +249,6 @@ void amd64_main(unsigned long bist)
                 enable_lapic();
                 init_timer();
 
-//                post_code(0x30);
 
 #if CONFIG_LOGICAL_CPUS==1
         #if ENABLE_APIC_EXT_ID == 1
@@ -276,12 +259,10 @@ void amd64_main(unsigned long bist)
         #endif
                 if(id.coreid == 0) {
                         if (cpu_init_detected(id.nodeid)) {
-//                                __asm__ volatile ("jmp __cpu_reset");
 				cpu_reset = 1;
 				goto cpu_reset_x;
                         }
                         distinguish_cpu_resets(id.nodeid);
-//                        start_other_core(id.nodeid);
                 }
 #else
         #if ENABLE_APIC_EXT_ID == 1
@@ -292,14 +273,12 @@ void amd64_main(unsigned long bist)
 
         #endif
                 if (cpu_init_detected(nodeid)) {
-//                        __asm__ volatile ("jmp __cpu_reset");
 			cpu_reset = 1;
 			goto cpu_reset_x;
                 }
                 distinguish_cpu_resets(nodeid);
 #endif
 
-//                post_code(0x31);
 
                 if (!boot_cpu()
 #if CONFIG_LOGICAL_CPUS==1 
@@ -312,13 +291,11 @@ void amd64_main(unsigned long bist)
                 }
         }
 
-//	post_code(0x32);
 	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
 
-//	dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
 	
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
@@ -332,17 +309,9 @@ void amd64_main(unsigned long bist)
 	needs_reset = setup_coherent_ht_domain();
 	
 #if CONFIG_LOGICAL_CPUS==1
-        // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
-#if 0
-
-	// You need to preset bus num in PCI_DEV(0, 0x18,1) 0xe0, 0xe4, 0xe8, 0xec
-        needs_reset |= ht_setup_chains(2);
-#else
-	// automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
-#endif
 
        	if (needs_reset) {
                	print_info("ht reset -\r\n");
@@ -360,29 +329,6 @@ void amd64_main(unsigned long bist)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-#if 0
-	dump_pci_devices();
-#endif
-
-        /* Check all of memory */
-#if 0
-        msr_t msr;
-        msr = rdmsr(TOP_MEM2);
-        print_debug("TOP_MEM2: ");
-        print_debug_hex32(msr.hi);
-        print_debug_hex32(msr.lo);
-        print_debug("\r\n");
-#endif
-#if 0
-        ram_check(0x00000000, msr.lo+(msr.hi<<32));
-#endif
-
-#if 0
-        // Check 16MB of memory @ 0
-        ram_check(0x00000000, 0x00100000);
-        // Check 16MB of memory @ 2GB 
-        ram_check(0x80000000, 0x80100000);
-#endif
 
 #if 1
         {
-- 
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