From 17d667b411685de57ea181cc496b29fea6d27d91 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Tue, 3 Apr 2007 10:45:53 +0000 Subject: Add initial framework for the Tyan S1846. It's not fully working, among other things because the Intel 440BX northbridge isn't working, yet. Signed-off-by: Uwe Hermann Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/tyan/s1846/Config.lb | 135 +++++++++++++++++++++++++++++++ src/mainboard/tyan/s1846/Options.lb | 150 +++++++++++++++++++++++++++++++++++ src/mainboard/tyan/s1846/auto.c | 86 ++++++++++++++++++++ src/mainboard/tyan/s1846/chip.h | 24 ++++++ src/mainboard/tyan/s1846/failover.c | 32 ++++++++ src/mainboard/tyan/s1846/mainboard.c | 26 ++++++ 6 files changed, 453 insertions(+) create mode 100644 src/mainboard/tyan/s1846/Config.lb create mode 100644 src/mainboard/tyan/s1846/Options.lb create mode 100644 src/mainboard/tyan/s1846/auto.c create mode 100644 src/mainboard/tyan/s1846/chip.h create mode 100644 src/mainboard/tyan/s1846/failover.c create mode 100644 src/mainboard/tyan/s1846/mainboard.c (limited to 'src/mainboard/tyan/s1846') diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb new file mode 100644 index 0000000000..c63d895de8 --- /dev/null +++ b/src/mainboard/tyan/s1846/Config.lb @@ -0,0 +1,135 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +# TODO. +chip northbridge/intel/i440bx + device pci_domain 0 on + end + chip cpu/intel/slot_2 + end +end + diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb new file mode 100644 index 0000000000..896a49d940 --- /dev/null +++ b/src/mainboard/tyan/s1846/Options.lb @@ -0,0 +1,150 @@ +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=0 +default IRQ_SLOT_COUNT=4 +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=9 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=9 + +default CONFIG_UDELAY_TSC=1 + +end + diff --git a/src/mainboard/tyan/s1846/auto.c b/src/mainboard/tyan/s1846/auto.c new file mode 100644 index 0000000000..26ed148b10 --- /dev/null +++ b/src/mainboard/tyan/s1846/auto.c @@ -0,0 +1,86 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "mainboard/bitworks/ims/debug.c" // FIXME +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "superio/nsc/pc87309/pc87309_early_serial.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = { + (0xa << 3) | 0, + (0xa << 3) | 1, + (0xa << 3) | 2, + (0xa << 3) | 3, + }, + }, + }; + + /* Skip this if there was a built in self test failure. */ + if (bist == 0) { + early_mtrr_init(); + } + + pc87309_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + enable_smbus(); + + dump_spd_registers(&memctrl[0]); + + sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + + /* Check 64 MB of RAM. */ + ram_check(0x00000000, 0x04000000); +} diff --git a/src/mainboard/tyan/s1846/chip.h b/src/mainboard/tyan/s1846/chip.h new file mode 100644 index 0000000000..f82ae70333 --- /dev/null +++ b/src/mainboard/tyan/s1846/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_tyan_s1846_ops; + +struct mainboard_tyan_s1846_config { +}; diff --git a/src/mainboard/tyan/s1846/failover.c b/src/mainboard/tyan/s1846/failover.c new file mode 100644 index 0000000000..bdcb9eaed2 --- /dev/null +++ b/src/mainboard/tyan/s1846/failover.c @@ -0,0 +1,32 @@ +#define ASSEMBLY 1 +#include +#include +#include +#include +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} diff --git a/src/mainboard/tyan/s1846/mainboard.c b/src/mainboard/tyan/s1846/mainboard.c new file mode 100644 index 0000000000..8ed2e5f457 --- /dev/null +++ b/src/mainboard/tyan/s1846/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "chip.h" + +struct chip_operations mainboard_tyan_s1846_ops = { + CHIP_NAME("Tyan S1846 Mainboard") +}; -- cgit v1.2.3