From 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 20 Nov 2010 10:31:00 +0000 Subject: Unify DIMM SPD addressing. For Geode, change the addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/traverse/geos/romstage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/traverse') diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index d5a00a4cbe..b3aff80af4 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -31,6 +31,7 @@ #include #include #include "southbridge/amd/cs5536/cs5536.h" +#include #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -43,8 +44,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #define ManualConf 1 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x0000059C /* manual settings for the PLL */ #define PLLMSRlo 0x00DE602E -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" -- cgit v1.2.3