From bbc880eee702fc175d4a3c3e87b682c26c38f940 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 20 Nov 2012 18:20:56 +0100 Subject: amdk8/amdfam10: Use CAR_GLOBAL for sysinfo This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Marc Jones --- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/technexion') diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 57cb3f23a8..bb8a3b1e0d 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -74,7 +74,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index ed133daf6e..4453f84455 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -72,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ -- cgit v1.2.3