From d63085b20ef40caae1c60a7532b5243e1e30b109 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Fri, 6 Nov 2009 17:11:05 +0000 Subject: Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb. Since we have CBFS setting rom_address in board files is no longer necessary. Also, drop vga_rom_address from RS690 completely, it was never used in the code. Signed-off-by: Uwe Hermann Acked-by: Myles Watson git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/technexion/tim8690/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mainboard/technexion/tim8690/devicetree.cb') diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb index b47e615e2d..10de5c16c8 100644 --- a/src/mainboard/technexion/tim8690/devicetree.cb +++ b/src/mainboard/technexion/tim8690/devicetree.cb @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,7 +22,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -33,7 +31,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" -- cgit v1.2.3