From bfb35f2488b9d392847df1e1d64c0f2fd1c7eccc Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 10 Mar 2023 13:28:53 -0700 Subject: mb/system76/tgl-u: Enable reporting CPU C10 state over eSPI This allows the EC to detect C10 using eSPI instead of a dedicated pin. Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494 Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689 Tested-by: build bot (Jenkins) --- src/mainboard/system76/tgl-u/variants/darp7/ramstage.c | 3 +++ src/mainboard/system76/tgl-u/variants/galp5/ramstage.c | 3 +++ src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c | 3 +++ 3 files changed, 9 insertions(+) (limited to 'src/mainboard/system76/tgl-u/variants') diff --git a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c index a60587d5d4..2b64f9f130 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/ramstage.c @@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[5] = 1; // J_TYPEC2 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } diff --git a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c index a60587d5d4..2b64f9f130 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/ramstage.c @@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[5] = 1; // J_TYPEC2 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c index 2064836977..8b80740294 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/ramstage.c @@ -12,4 +12,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // IOM config params->PchUsbOverCurrentEnable = 0; params->PortResetMessageEnable[2] = 1; // J_TYPEC1 + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } -- cgit v1.2.3