From 990d792ac71a4649d9a35bb01bdde98bb826e45b Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Sun, 17 Jul 2022 16:26:23 -0600 Subject: mb/system76/tgl-u: Convert galp5 to a variant Change-Id: I49185352002f6df2f9e9ab9c39d44cc9247b41b5 Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/64527 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../system76/tgl-u/variants/galp5/board_info.txt | 2 + .../system76/tgl-u/variants/galp5/data.vbt | Bin 0 -> 8704 bytes src/mainboard/system76/tgl-u/variants/galp5/gpio.c | 219 +++++++++++++++++++++ .../system76/tgl-u/variants/galp5/gpio_early.c | 16 ++ .../system76/tgl-u/variants/galp5/hda_verb.c | 26 +++ .../tgl-u/variants/galp5/include/variant/gpio.h | 13 ++ .../system76/tgl-u/variants/galp5/overridetree.cb | 201 +++++++++++++++++++ .../system76/tgl-u/variants/galp5/romstage.c | 22 +++ 8 files changed, 499 insertions(+) create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/board_info.txt create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/data.vbt create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/gpio.c create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb create mode 100644 src/mainboard/system76/tgl-u/variants/galp5/romstage.c (limited to 'src/mainboard/system76/tgl-u/variants') diff --git a/src/mainboard/system76/tgl-u/variants/galp5/board_info.txt b/src/mainboard/system76/tgl-u/variants/galp5/board_info.txt new file mode 100644 index 0000000000..0cd8c28778 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/board_info.txt @@ -0,0 +1,2 @@ +Board name: galp5 +Release year: 2020 diff --git a/src/mainboard/system76/tgl-u/variants/galp5/data.vbt b/src/mainboard/system76/tgl-u/variants/galp5/data.vbt new file mode 100644 index 0000000000..e3b164fd1d Binary files /dev/null and b/src/mainboard/system76/tgl-u/variants/galp5/data.vbt differ diff --git a/src/mainboard/system76/tgl-u/variants/galp5/gpio.c b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c new file mode 100644 index 0000000000..17119b3e75 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/gpio.c @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_GPI(GPD2, NONE, PWROK), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# - test point + PAD_CFG_GPO(GPD7, 1, PWROK), // GPD7_REST + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // GPD9_RTD3 + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), // SLP_S5# - test point + PAD_CFG_GPI(GPD11, UP_20K, DEEP), // LAN_DISABLE# + + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), // CNVI_RST# + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), // SATAGP1 + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), // 10K pull-up + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), // GPPC_A23_TBT_FORCE_PWR + + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + PAD_CFG_GPI(GPP_B2, UP_20K, DEEP), // VRALERT#_PD + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), // GPP_B3 - touchpad interrupt + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), // test point + PAD_NC(GPP_B6, NONE), // test point + PAD_NC(GPP_B7, NONE), + PAD_CFG_GPO(GPP_B8, 1, DEEP), // SB_BLON + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_GPO(GPP_B14, 0, DEEP), // PCH_SPKR + PAD_CFG_GPO(GPP_B15, 1, DEEP), // PCH_GPP_B15 - TODO + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), // No reboot strap + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), // PCH_GPP_B22 - 20k pull-down + PAD_CFG_GPO(GPP_B23, 0, DEEP), // Clock frequency strap + + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK and SMB_CLK_DDR + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA and SMB_DAT_DDR + PAD_NC(GPP_C2, NONE), // Intel AMT TLS strap + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_NC(GPP_C5, NONE), // Boot strap bit 0 + PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), // TBT-PCH_I2C_SCL + PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), // TBT-PCH_I2C_SDA + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + _PAD_CFG_STRUCT(GPP_C14, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL + //PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD + //PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_C22, 1, PLTRST), // LAN_PLT_RST# + _PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000), // PCH_GPP_C23 - 4.7k pull-down + + PAD_CFG_GPI(GPP_D0, NONE, DEEP), // DGPU_SELECT# + PAD_CFG_GPO(GPP_D1, 1, PLTRST), // GPU_EVENT# + PAD_CFG_GPI(GPP_D2, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_CFG_GPI(GPP_D3, NONE, PLTRST), // DGPU_PWRGD_R + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD1_CLKREQ# + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // PEG_CLKREQ# + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // CARD_CLKREQ# + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), // 4.7k pull-up + PAD_CFG_GPI(GPP_D11, DN_20K, DEEP), // BOARD_ID - low = GTX 1650Ti, high = GTX 1650 + PAD_CFG_GPI(GPP_D12, DN_20K, DEEP), // GPP_D12 - low = NVIDIA GPU, high = Intel GPU + PAD_CFG_GPO(GPP_D13, 0, DEEP), // dGPU_OVRM + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD1_PWR_DN# + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_GPI(GPP_D17, DN_20K, DEEP), // DGPU_PRSNT# + PAD_CFG_GPI(GPP_D18, DN_20K, DEEP), // 1V8_MAIN_EN_R + PAD_NC(GPP_D19, NONE), + + PAD_NC(GPP_E0, NONE), // test point + PAD_CFG_GPO(GPP_E1, 0, PLTRST), // ROM_I2C_EN + _PAD_CFG_STRUCT(GPP_E2, 0x40880100, 0x0000), // SWI# + PAD_CFG_GPI(GPP_E3, DN_20K, DEEP), // SCI# - unused, tunneled over eSPI + PAD_NC(GPP_E4, NONE), // test point + PAD_NC(GPP_E5, NONE), // DEVSLP1 + PAD_NC(GPP_E6, NONE), // PCH_GPP_E6 + _PAD_CFG_STRUCT(GPP_E7, 0x82840100, 0x0000), // SMI# + PAD_NC(GPP_E8, NONE), // PCH_SATAHDD_LED# + PAD_NC(GPP_E9, NONE), // 10k pull-up + PAD_NC(GPP_E10, NONE), // PCH_GPP_E10 + PAD_NC(GPP_E11, NONE), // PCH_GPP_E11 + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), // ALERT#_R + PAD_CFG_GPI(GPP_E16, DN_20K, DEEP), // SB_KBCRST# + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NONE), // TBT_LSX0_TXD - programmed by FSP, see Intel document 617016 + PAD_NC(GPP_E19, NONE), // TBT_LSX0_RXD - programmed by FSP, see Intel document 617016 + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), // CNVI_GNSS_PA_PLANKING - TODO + PAD_CFG_GPO(GPP_F7, 1, DEEP), // GPIO_LANRTD3 + PAD_NC(GPP_F8, NONE), + PAD_CFG_GPO(GPP_F9, 1, DEEP), // GPIO_LAN_EN + PAD_NC(GPP_F10, NONE), // 4.7k pull-up + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI(GPP_F17, NONE, PLTRST), // TPM_DET# + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_CFG_GPI(GPP_F21, DN_20K, DEEP), // EXT_PWR_GATE# - TODO + PAD_NC(GPP_F22, NONE), // VNN_CTRL - TODO + PAD_NC(GPP_F23, NONE), // 1P05_CTRL - TODO + + PAD_CFG_GPO(GPP_H0, 1, PLTRST), // GPP_H0_RTD3 + PAD_NC(GPP_H1, NONE), // 4.7k pull-up + PAD_NC(GPP_H2, NONE), // 4.7k pull-up + PAD_CFG_GPI(GPP_H3, DN_20K, DEEP), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // GPPH_I2C2_SDA + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // GPPH_I2C2_SCL + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), // SWI# - TODO + PAD_CFG_GPI(GPP_H8, DN_20K, DEEP), // CNVI_MFUART2_RXD - TODO + PAD_CFG_GPI(GPP_H9, DN_20K, DEEP), // CNVI_MFUART2_TXD - TODO + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), // CNVI_WAKE# + PAD_NC(GPP_H20, NONE), // PM_CLKRUN# + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), // GPPC_DMIC_CLK - TODO + PAD_NC(GPP_S7, NONE), // GPPC_DMIC_DATA - TODO + + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + + //PAD_CFG_GPO(GPP_U4, 0, DEEP), // DGPU_RST#_PCH + //PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c b/src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c new file mode 100644 index 0000000000..e2eb8483b3 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_U4, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c new file mode 100644 index 0000000000..1f21ff77e7 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15584018, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15584018), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h b/src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h new file mode 100644 index 0000000000..29a4dd22b8 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_U4 +#define DGPU_PWR_EN GPP_U5 +#define DGPU_GC6 GPP_D2 +#define DGPU_SSID 0x40181558 + +#endif diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb new file mode 100644 index 0000000000..1b4249c3f7 --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -0,0 +1,201 @@ +chip soc/intel/tigerlake + # Power limits + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 51, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 51, + }" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x4018 inherit + + device ref peg on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref north_xhci on # J_TYPEC2 + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # J_TYPEC2 + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1 + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1 CH0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1 CH1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port4 on end + end + end + end + end + device ref i2c2 on + # TODO: Pantone ROM? + register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" + end + device ref pcie_rp5 on + # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[2]" = "4" + register "PcieClkSrcClkReq[2]" = "2" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH + register "enable_delay_ms" = "16" + register "enable_off_delay_ms" = "4" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "4" + register "srcclk_pin" = "2" # PEG_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp9 on + # PCIe root port #9 x1, Clock 3 (CARD) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device ref pcie_rp10 on + # PCIe root port #10 x1, Clock 4 (GLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + register "PcieClkSrcUsage[4]" = "9" + register "PcieClkSrcClkReq[4]" = "4" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # GPIO_LANRTD3 + register "srcclk_pin" = "4" # LAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp11 on + # PCIe root port #11 x1, Clock 1 (WLAN) + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[10]" = "1" + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC2 + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + # SBU & HSL follow CC + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/system76/tgl-u/variants/galp5/romstage.c b/src/mainboard/system76/tgl-u/variants/galp5/romstage.c new file mode 100644 index 0000000000..eb4fd3974b --- /dev/null +++ b/src/mainboard/system76/tgl-u/variants/galp5/romstage.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} -- cgit v1.2.3