From daa4fb2ca2cab566e6a1c01f6edda65b34e2d4b9 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Tue, 27 Feb 2024 09:41:43 -0700 Subject: mb/system76/adl,rpl: Enable PchHdaSdiEnable Commit 4a58d14506ef ("soc/intel/alderlake: Hook up UPD PchHdaSdiEnable") and commit 2d482386182e ("soc/intel/alderlake: Set PchHdaSdiEnable for Alder Lake") hooked up this UPD in devicetree, causing the FSP default to be overridden (now disabled by default). Enable SDI to fix the following error: [DEBUG] PCI: 00:00:1f.3 init [DEBUG] azalia_audio: base = 0xbfbcc000 [DEBUG] azalia_audio: No codec! [DEBUG] PCI: 00:00:1f.3 init finished in 5 msecs Tested on gaze17-3050: Speaker output works again. Change-Id: Iceac1faec939ce9eea68c335929f96ec5f2bd132 Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/80754 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Jeremy Soller --- src/mainboard/system76/rpl/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/system76/rpl') diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index a016dec962..d389d2175b 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -66,6 +66,7 @@ chip soc/intel/alderlake device ref p2sb on end device ref hda on register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" register "pch_hda_idisp_codec_enable" = "1" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" -- cgit v1.2.3