From b1ef846da899c58c75f8ec1a98dd052dc4934dbf Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 23 Jun 2023 15:26:45 -0600 Subject: mb/system76/rpl: Add Galago Pro 7 as a variant The Galago Pro 7 (galp7) is a Raptor Lake-H board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Windows 10 and Linux 6.2 - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Not working: - Detection of devices in TBT slot on boot Change-Id: I1ae3b2c647aa75976a1ea97f7681f93eb000ba8a Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/75277 Reviewed-by: Jeremy Soller Tested-by: build bot (Jenkins) --- .../system76/rpl/variants/galp7/overridetree.cb | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 src/mainboard/system76/rpl/variants/galp7/overridetree.cb (limited to 'src/mainboard/system76/rpl/variants/galp7/overridetree.cb') diff --git a/src/mainboard/system76/rpl/variants/galp7/overridetree.cb b/src/mainboard/system76/rpl/variants/galp7/overridetree.cb new file mode 100644 index 0000000000..ee538fc2a7 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/galp7/overridetree.cb @@ -0,0 +1,84 @@ +chip soc/intel/alderlake + register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 78, + .tdp_pl4 = 90, + }" + + device domain 0 on + subsystemid 0x1558 0x4041 inherit + + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref tbt_pcie_rp0 on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + end + device ref tcss_dma0 on end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 (USB 3.2 Gen1) + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 (USB 3.2 Gen2) + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 (USB 3.2 Gen1) + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 (Thunerbolt) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2 (USB 3.2 Gen1) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1 (USB 3.2 Gen1) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 (USB 3.2 Gen2) + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref sata off end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp9 on + # PCIe RP#9 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp10 on + # PCIe RP#10 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + end +end -- cgit v1.2.3