From b7b5115360baa1ea0b9e8e554a12e9ac6da8fe87 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 1 Jul 2021 08:38:30 -0600 Subject: cannonlake mainboards: Set PMC as hidden in devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit FSP-S hides the PMC from the PCI bus when it runs, but there are still initialization steps coreboot programs for the PMC. Therefore, change all of the cannonlake mainboards to set the PMC as hidden in the devicetree, which means the device will be skipped during enumeration, but device callbacks are still issued as if the device were enabled. TEST=Ran full patch train on google/dratini, disassembled SSDT and the PEPD device matches what is in pep.asl. Also verified via dmesg that the INT33A1 device is still initialized by the kernel. Signed-off-by: Tim Wawrzynczak Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- src/mainboard/system76/oryp6/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/system76/oryp6') diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 24d894edbd..56b08fbb66 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -204,7 +204,7 @@ chip soc/intel/cannonlake end end device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller + device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" end -- cgit v1.2.3