From 3a5217a77b2561eb122d881581119753f2cd0039 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Tue, 26 Jul 2022 14:04:04 -0600 Subject: mb/system76/gaze16: Configure GPIOs in mainboard_init() Configure GPIOs in `mainboard_init()` instead of during FSP config. Change-Id: Icc40ce71d2bd104c5f41e992f9b28824a3b734d6 Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/66169 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard/system76/gaze16/variants/gaze16-3060') diff --git a/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c b/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c index 7422613308..0f83461ae4 100644 --- a/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c +++ b/src/mainboard/system76/gaze16/variants/gaze16-3060/ramstage.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "../../variant.h" +#include -void variant_silicon_init_params(FSP_S_CONFIG *params) +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + params->PchLegacyIoLowLatency = 1; + // PEG0 Config params->CpuPcieRpAdvancedErrorReporting[0] = 0; params->CpuPcieRpLtrEnable[0] = 1; -- cgit v1.2.3