From 45b6080561748fe579c8ee901811cf4043383c2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 8 Jan 2022 20:47:11 +0100 Subject: soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI bit set for any slots of already existing boards, add set the option PcieRpSlotImplemented=1 where appropriate. Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak --- src/mainboard/system76/gaze16/variants/3060/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/system76/gaze16/variants/3060') diff --git a/src/mainboard/system76/gaze16/variants/3060/overridetree.cb b/src/mainboard/system76/gaze16/variants/3060/overridetree.cb index 044df55457..7d5549935c 100644 --- a/src/mainboard/system76/gaze16/variants/3060/overridetree.cb +++ b/src/mainboard/system76/gaze16/variants/3060/overridetree.cb @@ -62,6 +62,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[7]" = "1" register "PcieClkSrcUsage[2]" = "7" register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" end device ref pcie_rp9 on # PCIe root port #9 x4, Clock 10 (SSD2) @@ -69,6 +70,7 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[10]" = "8" register "PcieClkSrcClkReq[10]" = "10" + register "PcieRpSlotImplemented[8]" = "1" end device ref gbe on end end -- cgit v1.2.3