From 2a404b599b3385b3246a2ee20844d2bc7a428035 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 7 Jan 2022 14:12:34 -0700 Subject: mb/system76: Enable SrcClk pin for CPU PCIe RPs This reverts commit bd9b044a96cc ("mb/system76: rtd3: Remove SrcClk pin on CPU RP"). Previously, RTD3 expected a PCH index for the root port and did not work with the CPU PCIe RP present on TGL, so SrcClk pin was disabled. Set them now that RTD3 supports mapping the index for the CPU RP. Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Jeremy Soller --- src/mainboard/system76/darp7/devicetree.cb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/system76/darp7') diff --git a/src/mainboard/system76/darp7/devicetree.cb b/src/mainboard/system76/darp7/devicetree.cb index 21f8141c5f..4b7ad233ea 100644 --- a/src/mainboard/system76/darp7/devicetree.cb +++ b/src/mainboard/system76/darp7/devicetree.cb @@ -113,8 +113,7 @@ chip soc/intel/tigerlake chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST# - # TODO: Support disable/enable CPU RP clock - register "srcclk_pin" = "-1" # SSD1_CLKREQ# + register "srcclk_pin" = "0" # SSD1_CLKREQ# device generic 0 on end end end -- cgit v1.2.3