From 976050113e4f4505579ae3001c9ddf8eeeeaa572 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Mon, 28 Nov 2022 09:30:23 -0700 Subject: mb/system76/adl-p: Disable SATA DevSlp After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in system76/ec@cc3effb6a451 ("board/system76/common: use SLP_S0# pin for modern standby detection"), DevSlp blocks suspend entry. Disable it until it is fixed. Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/70100 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller --- src/mainboard/system76/adl-p/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/system76/adl-p/devicetree.cb') diff --git a/src/mainboard/system76/adl-p/devicetree.cb b/src/mainboard/system76/adl-p/devicetree.cb index 6a9f362ac9..c7085b448b 100644 --- a/src/mainboard/system76/adl-p/devicetree.cb +++ b/src/mainboard/system76/adl-p/devicetree.cb @@ -73,7 +73,8 @@ chip soc/intel/alderlake device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 - register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + # FIXME: DevSlp breaks S0ix + #register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel -- cgit v1.2.3