From fe6526512a742c0bac2c1bbc919ee143ade3be06 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 26 Jul 2020 21:40:49 +0200 Subject: mb/supermicro/x11ssh-tf: Drop `PcieRpClkReqSupport` lines They default to zero already, so we might as well drop them. Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I3c04240b270f51d584f879e1344301679f133fdb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43928 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 50767bb35e..7996791a69 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -14,19 +14,15 @@ chip soc/intel/skylake # PCIe configuration # Enable JPCIE1 register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "0" # Enable ASpeed PCI bridge register "PcieRpEnable[2]" = "1" - register "PcieRpClkReqSupport[2]" = "0" # Enable X550T (10GbE) register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "0" # Enable M.2 register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "0" # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" -- cgit v1.2.3